公开(公告)号：US06620676B2

公开(公告)日：2003-09-16

申请号：US09895672

申请日：2001-06-29

申请人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

发明人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

摘要翻译： 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

公开(公告)号：US06579759B1

公开(公告)日：2003-06-17

申请号：US10227396

申请日：2002-08-23

申请人： Michael Patrick Chudzik ,  Jochen Beintner ,  Ramachandra Divakaruni ,  Rajarao Jammy

发明人： Michael Patrick Chudzik ,  Jochen Beintner ,  Ramachandra Divakaruni ,  Rajarao Jammy

IPC分类号： H01L218242

CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L29/66181

摘要： In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

摘要翻译： 在垂直晶体管DRAM单元中，通过以下方式解决了深沟槽电容器的节点与垂直晶体管的下电极之间可靠的电连接的问题; 沉积临时绝缘体层，在临时绝缘体上方的沟槽壁上形成垂直间隔物，然后剥离绝缘体以露出衬底壁; 将掺杂剂扩散到衬底壁中以形成埋入带的自对准延伸部; 沉积最后的栅极绝缘体; 然后形成DRAM单元的上部。

公开(公告)号：US06566228B1

公开(公告)日：2003-05-20

申请号：US10083744

申请日：2002-02-26

申请人： Jochen Beintner ,  Rama Divakaruni ,  Jack A. Mandelman ,  Andreas Knorr

发明人： Jochen Beintner ,  Rama Divakaruni ,  Jack A. Mandelman ,  Andreas Knorr

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/763 ,  H01L27/1052

摘要： Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

摘要翻译： 公开了一种同时提供用于由衬底材料制成的半导体衬底的阵列和支撑区域的沟槽隔离的方法，所述方法包括提供用于阵列和支撑区域的第一硬掩模层，所述第一硬掩模包括限定沟槽隔离的掩模开口 在阵列和支撑区域中，在阵列区域中提供深阵列沟槽隔离，在足以填充所述掩模开口和深阵列沟槽隔离的支撑和阵列区域上提供覆盖的平面化导电材料层，通过所述第一硬 掩模材料下降到所述半导体衬底中，以便形成支撑沟槽隔离，使得深阵列沟槽隔离和支撑沟槽隔离都具有相同的深度，并且其中包括一定数量的所述导电材料的导电元件保留在 每个所述深阵列沟槽。

公开(公告)号：US06534369B2

公开(公告)日：2003-03-18

申请号：US10062755

申请日：2002-01-31

申请人： Peter Thwaite ,  Jochen Beintner

发明人： Peter Thwaite ,  Jochen Beintner

IPC分类号： H01L21336

CPC分类号： H01L29/1033 ,  H01L21/76235

摘要： An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.

公开(公告)号：US06429092B1

公开(公告)日：2002-08-06

申请号：US09596606

申请日：2000-06-19

申请人： Jochen Beintner ,  Alexander Michaelis ,  Ulrike Gruening ,  Oswald Spindler ,  Zvonimir Gabric

发明人： Jochen Beintner ,  Alexander Michaelis ,  Ulrike Gruening ,  Oswald Spindler ,  Zvonimir Gabric

IPC分类号： H01L2176

CPC分类号： H01L27/10861 ,  H01L21/31612 ,  H01L21/32 ,  H01L27/1087

摘要： A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench in a silicon substrate, and depositing and recessing a nitride liner in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar in the trench.

摘要翻译： 根据本发明的在沟槽中形成氧化物环的方法包括在硅衬底中形成沟槽，以及在沟槽中沉积和凹陷氮化物衬垫以暴露沟槽侧壁上的硅衬底的一部分 。 对硅衬底的部分上的氮化物衬垫选择性地沉积氧化物。 从氮化物衬垫的表面去除残余氧化物，以在沟槽中形成环。

公开(公告)号：US06352893B1

公开(公告)日：2002-03-05

申请号：US09324927

申请日：1999-06-03

申请人： Alexander Michaelis ,  Stephan Kudelka ,  Jochen Beintner ,  Oliver Genz

发明人： Alexander Michaelis ,  Stephan Kudelka ,  Jochen Beintner ,  Oliver Genz

IPC分类号： H01L218242

CPC分类号： H01L21/02238 ,  C25D11/32 ,  H01L21/02258 ,  H01L21/31675 ,  H01L27/10861

摘要： A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.

摘要翻译： 根据本发明的用于制造半导体器件的方法包括以下步骤：提供具有暴露的p掺杂硅区域的半导体晶片并将晶片放置在电化学电池中，使得包含电解质的溶液与暴露的p掺杂硅区域相互作用， 当在晶片和溶液之间提供电位差时，掺杂的硅区域在暴露的p掺杂的硅区域上形成氧化物。

公开(公告)号：US06323103B1

公开(公告)日：2001-11-27

申请号：US09175267

申请日：1998-10-20

申请人： Rajesh Rengarajan ,  Jochen Beintner ,  Ulrike Gruening ,  Hans-Oliver Joachim

发明人： Rajesh Rengarajan ,  Jochen Beintner ,  Ulrike Gruening ,  Hans-Oliver Joachim

IPC分类号： H01L218238

CPC分类号： H01L21/823878 ,  H01L21/762

摘要： A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.

摘要翻译： 提供了一种用于在半导体主体的不同电隔离有源区中制造第一和第二MOSFET晶体管的方法，每个晶体管具有多个层。 第一栅极氧化物层和第一多晶硅层沉积在半导体主体上方的有源区域上。 在所述第一栅极氧化物和多晶硅层和所述半导体本体中蚀刻沟槽以描绘第一和第二有源区，从而形成与第一有源区共同延伸的第一划定的栅极氧化物层和多晶硅层。 材料沉积在所述沟槽中以形成有源区隔离，所述有源区隔离在所述半导体本体上方具有顶表面。 然后在所述第一和第二有源区上形成掩模层，并且去除其选择性部分以暴露所述第二有源区。 屏蔽层和有源区隔离一起形成掩模，其限定与第二有源区域共同延伸的开口，其中限定所述开口的有源区隔离。 通过开口的材料形成第二栅氧化层和第二多晶层，这种第二层和第二多晶层与第二有源区共同延伸。 第一晶体管，其具有第一划定的栅极氧化物和多晶层作为第一晶体管的多个层和第二晶体管的一对，其中第二栅极氧化物层和第二多晶层作为一对多个层 的第二晶体管。