公开(公告)号：US20180107537A1

公开(公告)日：2018-04-19

申请号：US15784746

申请日：2017-10-16

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F11/07

Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

公开(公告)号：US20170364609A1

公开(公告)日：2017-12-21

申请号：US15340638

申请日：2016-11-01

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F17/50 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F17/504 ,  G06F9/30145 ,  G06F9/3802 ,  G06F11/076 ,  G06F11/3055 ,  G06F17/5022 ,  G06F2217/14

Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.

公开(公告)号：US20170344503A1

公开(公告)日：2017-11-30

申请号：US15680755

申请日：2017-08-18

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari

IPC: G06F13/364 ,  G06F13/36 ,  G06F11/30 ,  G06F11/28 ,  G06F9/46 ,  G06F13/42 ,  G06F5/00

CPC classification number: G06F13/364 ,  G06F5/00 ,  G06F9/467 ,  G06F11/28 ,  G06F11/30 ,  G06F13/36 ,  G06F13/4282

Abstract: Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions for each master using the one or more counters; and control logic that verifies that a transaction response for an in-flight transaction for a particular master has been issued by the slave in a predetermined order based on the tracked age for the in-flight transaction in the table.

公开(公告)号：US09563727B2

公开(公告)日：2017-02-07

申请号：US14674555

申请日：2015-03-31

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari

IPC: G06F17/50 ,  G01R31/317

CPC classification number: G06F17/5031 ,  G01R31/31727 ,  G06F17/504 ,  G06F17/5081

Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.

Abstract translation: 使用基于断言的验证来验证导出时钟的方法和系统。 该方法包括计数在慢时钟的上升沿和下降沿之间（即，在慢时钟的接通阶段）期间发生的快速时钟的全周期或半周期的数量; 计数在慢时钟的下降沿和上升沿之间（即在慢时钟的OFF阶段期间）发生的快时钟的全周期或半周期的数量; 并使用基于断言的验证来验证计数。