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    SM3 HASH FUNCTION MESSAGE EXPANSION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    81.
    发明申请
    SM3 HASH FUNCTION MESSAGE EXPANSION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    SM3 HASH功能消息扩展处理器，方法，系统和指令

    公开(公告)号：US20150186139A1

    公开(公告)日：2015-07-02

    申请号：US14142745

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali ,  Sean Gulley

    IPC: G06F9/30

    CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/30036 ,  G09C1/00 ,  H04L9/0643 ,  H04L2209/122

    Abstract: A processor includes a decode unit to receive an instruction to indicate a first source packed data operand and a second source packed data operand. The source operands each to include elements. The data elements to include information selected from messages and logical combinations of messages that is sufficient to evaluate: P1(Wj−16 XOR Wj−9 XOR(Wj−3

    Abstract translation: 处理器包括解码单元，用于接收指示第一源打包数据操作数和第二源打包数据操作数的指令。 每个源操作数包含元素。 数据元素包括从消息中选择的信息和足以评估的消息的逻辑组合：P1（Wj-16 XOR Wj-9 XOR（Wj-3 <<<15））XOR（Wj-13 <<<7） XOR Wj-6 P1是置换函数，P1（X）= X XOR（X <<<15）XOR（X <<< 23）。 Wj-16，Wj-9，Wj-3，Wj-13和Wj-6是与SM3散列函数的压缩函数相关联的消息。 XOR是异或运算。 <<<是旋转操作。 与解码单元耦合的执行单元，其可响应于该指令操作以将结果打包数据存储在目的地存储位置中。 结果打包数据以包括要输入到压缩函数的第j个的Wj消息。

    Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality
    83.
    发明授权
    Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality 有权

    公开(公告)号：US11303438B2

    公开(公告)日：2022-04-12

    申请号：US16928558

    申请日：2020-07-14

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

    Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

    Techniques to accelerate lossless compression
    86.
    发明授权
    Techniques to accelerate lossless compression 有权

    公开(公告)号：US10158376B2

    公开(公告)日：2018-12-18

    申请号：US15053921

    申请日：2016-02-25

    Applicant: INTEL CORPORATION

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Wajdi K. Feghali

    IPC: H03M7/00 ,  H03M7/30 ,  G06F9/30

    Abstract: An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a data structure at least one position of at least one subset of characters that are to be encoded as a symbol, (b) comparing, at least in part, at least one pair of multi-byte data words that are of identical predetermined fixed size, (c) maintaining, at least in part, an array of pointers to potentially matching strings that are to be compared with at least one currently examined string, and/or (d) allocating, at least in part, a first buffer portion to store at least one portion of uncompressed data from an application buffer that is to be input for compression to produce a compressed data stream.

    Instruction and logic to provide SIMD secure hashing round slice functionality
    88.
    发明授权
    Instruction and logic to provide SIMD secure hashing round slice functionality 有权

    公开(公告)号：US10148428B2

    公开(公告)日：2018-12-04

    申请号：US14568101

    申请日：2014-12-11

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap

    IPC: G06F11/30 ,  H04L9/06 ,  G06F21/64 ,  G06F21/60 ,  G06F9/30 ,  G06F9/38 ,  G06F15/80

    Abstract: Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

    Supporting data compression using match scoring
    90.
    发明授权
    Supporting data compression using match scoring 有权

    公开(公告)号：US10140046B2

    公开(公告)日：2018-11-27

    申请号：US15663328

    申请日：2017-07-28

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/34 ,  G06F3/06 ,  H03M7/40 ,  H03M7/30 ,  G06F8/52 ,  G06F12/1018 ,  G06F12/1027

    Abstract: A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.

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