公开(公告)号：US11088951B2

公开(公告)日：2021-08-10

申请号：US15638102

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ren Wang ,  Tsung-Yuan C. Tai ,  Yipeng Wang ,  Sameh Gobriel

IPC: H04L12/743 ,  H04L12/851 ,  H04L12/741 ,  H04L29/12 ,  H04L12/751

Abstract: Apparatus, methods, and systems for tuple space search-based flow classification using cuckoo hash tables and unmasked packet headers are described herein. A device can communicate with one or more hardware switches. The device can include memory to store hash table entries of a hash table. The device can include processing circuitry to perform a hash lookup in the hash table. The lookup can be based on an unmasked key include in a packet header corresponding to a received data packet. The processing circuitry can retrieve an index pointing to a sub-table, the sub-table including a set of rules for handling the data packet. Other embodiments are also described.

公开(公告)号：US10904161B2

公开(公告)日：2021-01-26

申请号：US16218262

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Ren Wang ,  Ahmad A. Samih ,  Christian Maciocco ,  Andrew Brown ,  Tsung-Yuan C. Tai

IPC: H04L12/801 ,  H04L12/24 ,  H04L5/14 ,  H04W84/18 ,  H04L12/927 ,  H04L12/725 ,  H04L12/931 ,  H04L12/863 ,  H04L12/851 ,  H04L12/841

Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for routing data packets in a quality of service (QoS) enabled content-based network or interconnect fabric. Various embodiments describe how to manage data flow based on content-based attribute vectors (AVs) indicating QoS requirements with respect to the data packets in networking or platform interconnects. A dynamic scheduling based on AV information may improve trafficking efficiency and optimize system performance.

公开(公告)号：US10805229B2

公开(公告)日：2020-10-13

申请号：US16410442

申请日：2019-05-13

Applicant: Intel Corporation

Inventor： Ren Wang ,  Tsung-Yuan Charles Tai ,  Jr-Shian Tsai

IPC: H04L12/925 ,  H04L12/911 ,  H04N1/333 ,  H04L1/18 ,  H04L12/835 ,  H04L12/12 ,  H04L29/08

Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

公开(公告)号：US20200285578A1

公开(公告)日：2020-09-10

申请号：US16822939

申请日：2020-03-18

Applicant: Intel Corporation

Inventor： Ren Wang ,  Joseph Nuzman ,  Samantika S. Sury ,  Andrew J. Herdrich ,  Namakkal N. Venkatesan ,  Anil Vasudevan ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

Abstract: Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

公开(公告)号：US10552153B2

公开(公告)日：2020-02-04

申请号：US15476302

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ren Wang ,  Chunhui Zhang ,  Qixiong J. Bian ,  Bret L. Toll ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0891 ,  G06F13/28 ,  G06F12/084

Abstract: Method and apparatus for efficient range-based memory write back is described herein. One embodiment of an apparatus includes a system memory, a plurality of hardware processor cores each of which includes a first cache, a decoder circuitry to decode an instruction having fields for a first memory address and a range indicator, and an execution circuitry to execute the decoded instruction. Together, the first memory address and the range indicator define a contiguous region in the system memory that includes one or more cache lines. An execution of the decoded instruction causes any instances of the one or more cache lines in the first cache to be invalidated. Additionally, any invalidated instances of the one or more cache lines that are dirty are to be stored to system memory.

公开(公告)号：US10445271B2

公开(公告)日：2019-10-15

申请号：US14987676

申请日：2016-01-04

Applicant: Intel Corporation

Inventor： Ren Wang ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Yipeng Wang ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs ,  Andrew J. Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson

IPC: G06F13/37 ,  G06F12/0811 ,  G06F13/16 ,  G06F12/0868 ,  G06F12/04 ,  G06F9/38

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US10313240B2

公开(公告)日：2019-06-04

申请号：US15632592

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Sameh Gobriel ,  Wei Shen ,  Tsung-Yuan C. Tai ,  Ren Wang

IPC: H04L12/927 ,  H04L12/743 ,  H04L12/741 ,  H04L29/12 ,  H04L12/755

Abstract: Technologies for efficient network flow classification include a computing device that receives a network packet that includes a header. The computing device generates a vector Bloom filter (VBF) key as a function of the header and searches multiple VBFs for a VBF that matches the VBF key. Each VBF is associated with a flow sub-table that includes one or more flow rules. Each flow sub-table is associated with a mask length. If a matching VBF is found, the computing device searches the corresponding flow sub-table for a flow rule that matches a masked header of the network packet. If no matching VBF is found or if no matching flow rule is found, the computing device searches all of the flow sub-tables for a flow rule that matches the header. The computing device applies a flow action of a matching flow rule. Other embodiments are described and claimed.

公开(公告)号：US20190012200A1

公开(公告)日：2019-01-10

申请号：US15645226

申请日：2017-07-10

Applicant: INTEL CORPORATION

Inventor： Christopher B. Wilkerson ,  Karl I. Taht ,  Ren Wang ,  James J. Greensky ,  Tsung-Yuan C. Tai

IPC: G06F9/48

Abstract: A computing platform, including: an execution unit to execute a program, the program including a first phase and a second phase; and a quick response module (QRM) to: receive a program phase signature for the first phase; store the program phase signature in a pattern match action (PMA) table; identify entry of the program into the first phase via the PMA; and apply an optimization to the computing platform.

公开(公告)号：US20190004958A1

公开(公告)日：2019-01-03

申请号：US15640060

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US10145694B2

公开(公告)日：2018-12-04

申请号：US14368350

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Ren Wang ,  Zhonghong Ou ,  Arvind Kumar ,  Kristoffer Fleming ,  Tsung-Yuan C. Tai ,  Timothy J. Gresham ,  John C. Weast ,  Corey Kukis

IPC: G01C21/34 ,  H04B17/318 ,  H04W24/08 ,  H04W4/02

Abstract: Technologies for providing information to a user while traveling include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data. Other embodiments are described and claimed.