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1.
公开(公告)号:US11943340B2
公开(公告)日:2024-03-26
申请号:US17437342
申请日:2019-04-19
Applicant: Intel Corporation
Inventor: Bo Cui , Cunming Liang , Jr-Shian Tsai , Ping Yu , Xiaobing Qian , Xuekun Hu , Lin Luo , Shravan Nagraj , Xiaowen Zhang , Mesut A. Ergin , Tsung-Yuan C. Tai , Andrew J. Herdrich
CPC classification number: H04L9/0825 , H04L9/0631 , H04L9/085 , H04L63/0236
Abstract: In some examples, for process-to-process communication, such as in function linking, a virtual channel can be provisioned to provide virtual machine to virtual machine communications. In response to a transmit request from a source virtual machine, the virtual channel can cause a data copy from a source buffer associated with the source virtual machine without decryption or encryption. The virtual channel provisions a key identifier for the copied data. The destination virtual machine can receive an indication data is available and can cause the data to be decrypted using a key accessed using the key identifier and source address of the copied data. In addition, the data can be encrypted using a second, different key for storage in a destination buffer associated with the destination virtual machine. In some examples, the key identifier and source address is managed by the virtual channel and is not visible to virtual machine or hypervisor.
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公开(公告)号:US11829789B2
公开(公告)日:2023-11-28
申请号:US17671093
申请日:2022-02-14
Applicant: Intel Corporation
Inventor: Ashok Sunder Rajan , Richard A. Uhlig , Rajendra S. Yavatkar , Tsung-Yuan C. Tai , Christian Maciocco , Jeffrey R. Jackson , Daniel J. Dahle
CPC classification number: G06F9/45533 , G06F9/455 , G06F9/45537 , G06F9/5077 , H04L41/00 , G06F9/445
Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
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公开(公告)号:US11797076B2
公开(公告)日:2023-10-24
申请号:US17364523
申请日:2021-06-30
Applicant: Intel Corporation
Inventor: Brian J. Skerry , Ira Weiny , Patrick Connor , Tsung-Yuan C. Tai , Alexander W. Min
IPC: G06F1/3234 , G06F1/3209 , H04L49/00 , H04L49/40
CPC classification number: G06F1/3243 , G06F1/3209 , H04L49/40 , H04L49/70 , Y02D10/00
Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.
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公开(公告)号:US20230030060A1
公开(公告)日:2023-02-02
申请号:US17838872
申请日:2022-06-13
Applicant: Intel Corporation
Inventor: Ren Wang , Mia PRIMORAC , Tsung-Yuan C. Tai , Saikrishna EDUPUGANTI , John J. Browne
Abstract: Technologies for dynamically managing a batch size of packets include a network device. The network device is to receive, into a queue, packets from a remote node to be processed by the network device, determine a throughput provided by the network device while the packets are processed, determine whether the determined throughput satisfies a predefined condition, and adjust a batch size of packets in response to a determination that the determined throughput satisfies a predefined condition. The batch size is indicative of a threshold number of queued packets required to be present in the queue before the queued packets in the queue can be processed by the network device.
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公开(公告)号:US11379342B2
公开(公告)日:2022-07-05
申请号:US16827410
申请日:2020-03-23
Applicant: Intel Corporation
Inventor: Ren Wang , Bin Li , Andrew J. Herdrich , Tsung-Yuan C. Tai , Ramakrishna Huggahalli
IPC: G06F11/30 , G06F11/34 , G06F12/0811 , G06F12/121 , G06F13/16 , G06F13/42 , G06F12/128 , G06F12/084 , G06F12/0888 , H04L67/1097 , G06F13/28
Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a selected cache level; and a cache monitoring circuit, including a cache counter to track cache lines evicted from the selected cache level without being processed; and logic to provide a direct write policy according to the cache counter.
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公开(公告)号:US20210180965A1
公开(公告)日:2021-06-17
申请号:US16941163
申请日:2020-07-28
Applicant: Intel Corporation
Inventor: Ren Wang , Zhonghong Ou , Arvind Kumar , Kristoffer Fleming , Tsung-Yuan C. Tai , Timothy J. Gresham , John C. Weast , Corey Kukis
IPC: G01C21/34 , H04W4/024 , H04W4/029 , H04B17/318 , H04W24/08
Abstract: Technologies for providing information to a user while traveling include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data. Other embodiments are described and claimed.
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公开(公告)号:US10339023B2
公开(公告)日:2019-07-02
申请号:US14496216
申请日:2014-09-25
Applicant: Intel Corporation
Inventor: Ren Wang , Tsung-Yuan C. Tai , Paul S. Diefenbaugh , Andrew J. Herdrich
IPC: G06F12/084 , G06F11/30 , G06F11/34 , G06F12/0895 , G06F1/3206 , G06F1/3234 , G06F1/3287
Abstract: In one embodiment, a processor includes: a plurality of cores each to independently execute instructions; a shared cache memory coupled to the plurality of cores and having a plurality of clusters each associated with one or more of the plurality of cores; a plurality of cache activity monitors each associated with one of the plurality of clusters, where each cache activity monitor is to monitor one or more performance metrics of the corresponding cluster and to output cache metric information; a plurality of thermal sensors each associated with one of the plurality of clusters and to output thermal information; and a logic coupled to the plurality of cores to receive the cache metric information from the plurality of cache activity monitors and the thermal information and to schedule one or more threads to a selected core based at least in part on the cache metric information and the thermal information for the cluster associated with the selected core. Other embodiments are described and claimed.
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公开(公告)号:US10284470B2
公开(公告)日:2019-05-07
申请号:US14580801
申请日:2014-12-23
Applicant: Intel Corporation
Inventor: Ren Wang , Namakkal N. Venkatesan , Aamer Jaleel , Tsung-Yuan C. Tai , Sameh Gobriel , Christian Maciocco
IPC: H04L12/743 , H04L29/06 , H04L12/747
Abstract: Technologies for managing network flow lookups of a network device include a network controller and a target device, each communicatively coupled to the network device. The network device includes a cache for a processor of the network device and a main memory. The network device additionally includes a multi-level hash table having a first-level hash table stored in the cache of the network device and a second-level hash table stored in the main memory of the network device. The network device is configured to determine whether to store a network flow hash corresponding to a network flow indicating the target device in the first-level or second-level hash table based on a priority of the network flow provided to the network device by the network controller.
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公开(公告)号:US20190104150A1
公开(公告)日:2019-04-04
申请号:US15720821
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Sameh Gobriel , Christian Maciocco , Byron Marohn , Ren Wang , Tsung-Yuan C. Tai
Abstract: A computing apparatus for providing a node within a distributed network function, including: a hardware platform; a network interface to communicatively couple to at least one other peer node of the distributed network function; a distributor function including logic to operate on the hardware platform, including a hashing module configured to receive an incoming network packet via the network interface and perform on the incoming network packet a first-level hash of a two-level hash, the first level hash being a lightweight hash with respect to a second-level hash, the first level hash to deterministically direct a packet to one of the nodes of the distributed network function as a directed packet; and a denial of service (DoS) mitigation engine to receive notification of a DoS attack, identify a DoS packet via the first-level hash, and prevent the DoS packet from reaching the second-level hash.
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10.
公开(公告)号:US20180373633A1
公开(公告)日:2018-12-27
申请号:US15634785
申请日:2017-06-27
Applicant: Intel Corporation
Inventor: Andrew J. Herdrich , Edwin Verplanke , Stephen R. Van Doren , Ravishankar Iyer , Eric R. Wehage , Rupin H. Vakharwala , Rajesh M. Sankaran , Jeffrey D. Chamberlain , Julius Mandelblat , Yen-Cheng Liu , Stephen T. Palermo , Tsung-Yuan C. Tai
IPC: G06F12/0811 , G06F13/42 , G06F9/455 , G06F9/50 , G06F12/1009 , G06F13/16
Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.
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