公开(公告)号：US20190386934A1

公开(公告)日：2019-12-19

申请号：US16554064

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Ilango Ganga ,  Alain Gravel ,  Thomas Lovett ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson

IPC: H04L12/939 ,  H04L12/947 ,  H04L1/16

Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.

公开(公告)号：US10404625B2

公开(公告)日：2019-09-03

申请号：US14496667

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Ilango Ganga ,  Alain Gravel ,  Thomas Lovett ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson

IPC: H04L12/939 ,  H04L1/16 ,  H04L12/947 ,  H04L12/861

Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fiber Channel and/or other proprietary technologies, etc.

公开(公告)号：US09674098B2

公开(公告)日：2017-06-06

申请号：US14313740

申请日：2014-06-24

Applicant: INTEL CORPORATION

Inventor： Ilango Ganga ,  Alain Gravel ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson ,  Thomas D. Lovett

IPC: H04L1/00 ,  H04L12/851

CPC classification number: H04L47/2441 ,  Y02D30/30 ,  Y02D30/32

Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.

公开(公告)号：US12111775B2

公开(公告)日：2024-10-08

申请号：US17212722

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Duane E. Galbi ,  Matthew J. Adiletta ,  Hugh Wilkinson ,  Patrick Connor

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1621 ,  G06F13/1668 ,  G06F13/409 ,  G06F13/4221

Abstract: Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub. In some examples, based on provision of the at least some but not all home agent operations to be performed by the second home agent, the second home agent is to perform the at least some but not all home agent operations.

公开(公告)号：US20180095892A1

公开(公告)日：2018-04-05

申请号：US15283355

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Hugh Wilkinson ,  William R. Wheeler ,  Shirish Aundhe ,  Sandhya Viswanathan ,  David A. Koufaty

IPC: G06F12/1027 ,  G06F12/14 ,  G06F9/30

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30145 ,  G06F12/145 ,  G06F2212/1052 ,  G06F2212/68

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate source memory address information, and the instruction to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result is to include one of: (1) a page group identifier that is to correspond to a logical memory address that is to be based, at least in part, on the source memory address information; and (2) a set of page group metadata that is to correspond to the page group identifier. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20180004655A1

公开(公告)日：2018-01-04

申请号：US15201303

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Hugh Wilkinson ,  William R. Wheeler ,  Debra Bernstein

IPC: G06F12/02 ,  G11C7/10

Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US11134021B2

公开(公告)日：2021-09-28

申请号：US15394488

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Jonathan Kenny ,  Niall D. McDonnell ,  Andrew Cunningham ,  Debra Bernstein ,  William G. Burroughs ,  Hugh Wilkinson

IPC: H04L12/863 ,  G06F13/00 ,  H04L12/801

Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

公开(公告)号：US11063884B2

公开(公告)日：2021-07-13

申请号：US16554064

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Ilango Ganga ,  Alain Gravel ,  Thomas Lovett ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson

IPC: H04L12/939 ,  H04L1/16 ,  H04L12/947 ,  H04L12/861

Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.

公开(公告)号：US10929323B2

公开(公告)日：2021-02-23

申请号：US16601137

申请日：2019-10-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Andrew Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC: G06F13/37 ,  G06F9/54 ,  G06F12/0868 ,  G06F12/0811 ,  G06F13/16 ,  G06F12/04 ,  G06F9/38

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US10523796B2

公开(公告)日：2019-12-31

申请号：US14979179

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Hugh Wilkinson ,  James C. Wright

IPC: H04L12/947 ,  H04L12/933 ,  H04L29/06 ,  H04L29/12 ,  H04L12/931 ,  H04L12/46 ,  H04L12/721 ,  H04L12/937

Abstract: Techniques for embedding fabric addressing information within Ethernet media access control (MAC) addresses is disclosed herein and allows a multi-node fabric having potentially millions of nodes to feature Ethernet encapsulation without the necessity of a lookup or map to translate MAC addresses to fabric-routable local identifiers (LIDs). In particular, a locally-administered MAC address may be encoded with fabric addressing information including a LID. Thus a node may exchange Ethernet packets using a multi-node fabric by encapsulating each Ethernet packet with a destination MAC address corresponding to an intended destination. As the destination MAC address may implicitly map to a LID of the multi-node fabric, the node may use an extracted LID value therefrom to address a fabric-routable packet. To this end, a node may introduce a fabric-routable packet encapsulating an Ethernet packet onto a multi-node fabric without necessarily performing a lookup to map a MAC address to a corresponding LID.