公开(公告)号：US20130021305A1

公开(公告)日：2013-01-24

申请号：US13186281

申请日：2011-07-19

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Jonghae Kim

IPC分类号： G09G5/00 ,  H01L41/22 ,  H01L41/047

CPC分类号： H03H9/02228 ,  H03H3/02 ,  H03H9/02055 ,  H03H9/173 ,  H03H2003/021 ,  Y10T29/42

摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a resonator structure includes a first conductive layer of electrodes and a second conductive layer of electrodes. A piezoelectric layer including a piezoelectric material is disposed between the first conductive layer and the second conductive layer. One or more trenches can be formed in the piezoelectric layer on one or both sides in space regions between the electrodes. In some implementations, a process for forming the resonator structure includes removing an exposed portion of the piezoelectric layer to define a trench, for instance, by partial etching or performing an isotropic release etch using a XeF2 gas or SF6 plasma. In some other implementations, a portion of a sacrificial layer is removed to define a trench in the piezoelectric layer.

摘要翻译： 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 一方面，谐振器结构包括电极的第一导电层和电极的第二导电层。 包括压电材料的压电层设置在第一导电层和第二导电层之间。 一个或多个沟槽可以在电极之间的空间区域的一侧或两侧的压电层中形成。 在一些实施方案中，用于形成谐振器结构的工艺包括去除压电层的暴露部分以限定沟槽，例如通过部分蚀刻或使用XeF 2气体或SF 6等离子体进行各向同性释放蚀刻。 在一些其他实施方案中，去除牺牲层的一部分以在压电层中限定沟槽。

公开(公告)号：US08359421B2

公开(公告)日：2013-01-22

申请号：US12536991

申请日：2009-08-06

申请人： Feng Wang ,  Matthew Michael Nowak ,  Jonghae Kim

发明人： Feng Wang ,  Matthew Michael Nowak ,  Jonghae Kim

IPC分类号： G06F13/00 ,  G06F12/00 ,  G06F15/16

CPC分类号： G06F13/1663 ,  G06F13/1684 ,  Y02D10/14

摘要： A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters.

摘要翻译： 一种方法包括从多个主器件识别第一组主器件和第二组主器件。 多个主机通过交叉开关互连访问多通道存储器。 该方法包括将交叉开关互连划分成多个分区，其包括至少对应于第一组主机的第一分区和对应于第二组主机的第二分区。 该方法还包括在多通道存储器内分配第一组缓冲区。 第一组缓冲区对应于第一组主机。 该方法还包括在多通道存储器内分配第二组缓冲区。 第二组缓冲器对应于第二组主机。

公开(公告)号：US08148953B2

公开(公告)日：2012-04-03

申请号：US11946550

申请日：2007-11-28

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James Randal Moulic

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James Randal Moulic

IPC分类号： H02J7/00

CPC分类号： H02J7/345

摘要： An apparatus and method for recycling and reusing charge in an electronic circuit. The apparatus includes at least one capacitor coupled to a circuit block in the electronic circuit, the capacitor being configured to collect current charge consumed by the circuit block when set to a charge collection mode, and a voltage level comparator configured to detect a fully charged state when the capacitor is fully charged. Further, the apparatus includes a first electrical switch configured to allow, once the fully charged state is detected, the capacitor to switch to a discharge mode for discharging the current charge collected back into the power supply for reuse by the electrical system and a second switch configured to allow, after the capacitor has fully discharged the current charge collected, the capacitor to switch back to the charge collection mode, such that, the current charge is recycled and reused by the electrical system.

摘要翻译： 一种用于在电子电路中再循环和再利用电荷的装置和方法。 该装置包括耦合到电子电路中的电路块的至少一个电容器，电容器被配置为当设置为电荷收集模式时收集由电路块消耗的当前电荷;以及电压电平比较器，被配置为检测完全充电状态 当电容器充满电时。 此外，该装置包括第一电开关，其被配置为允许一旦检测到完全充电状态，电容器切换到放电模式，用于将收集的当前电荷放回电源供电系统和第二开关 配置为允许在电容器已经完全放电所收集的当前电荷之后，电容器切换回电荷收集模式，使得当前电荷被电气系统再循环和再利用。

公开(公告)号：US08094706B2

公开(公告)日：2012-01-10

申请号：US11733318

申请日：2007-04-10

申请人： Dae Ik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic ,  Hong Hua Song

发明人： Dae Ik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic ,  Hong Hua Song

IPC分类号： H04B3/46 ,  H04B17/00 ,  H04Q1/20

CPC分类号： G06F11/008

摘要： Method, system and article of manufacture are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades to or past a specified threshold. The technique includes periodically determining a maximum frequency of operation of the digital system, and generating a warning signal indicative of a reliability degradation of the digital system if at least one of: (i) a measured or estimated maximum frequency of operation of the digital system is below a warning threshold frequency of operation of the digital system, wherein the warning threshold frequency is greater than or equal to a manufacturer specified minimum frequency of operation for the digital system; or (ii) a rate of change in the difference between measured maximum frequencies of operation of the digital system exceeds an acceptable rate of change threshold for the digital system.

摘要翻译： 提供了方法，系统和制造品，用于连续监视数字系统的可靠性或老化，并且如果数字系统操作降低到或超过指定阈值，则发出警告信号。 该技术包括周期性地确定数字系统的最大操作频率，以及产生指示数字系统的可靠性劣化的警告信号，如果以下至少一个：（i）数字系统的测量或估计的最大操作频率 低于数字系统的警告阈值操作频率，其中警告阈值频率大于或等于制造商规定的数字系统的最小操作频率; 或者（ii）数字系统的测量的最大操作频率之间的差异的变化率超过数字系统的可接受的变化率阈值。

公开(公告)号：US08039354B2

公开(公告)日：2011-10-18

申请号：US12849086

申请日：2010-08-03

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Jonghae Kim ,  Jean-Oliver Plouchart ,  Anthony K. Stamper

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Jonghae Kim ,  Jean-Oliver Plouchart ,  Anthony K. Stamper

IPC分类号： H01L21/02

CPC分类号： H01L23/5228 ,  H01L23/5227 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.

摘要翻译： 通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。 电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。 电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

公开(公告)号：US08037340B2

公开(公告)日：2011-10-11

申请号：US11946466

申请日：2007-11-28

申请人： Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James Randal Moulic

发明人： Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James Randal Moulic

IPC分类号： G06F1/04

CPC分类号： G06F1/08

摘要： An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency.

摘要翻译： 一种用于微调微处理器中的核心的有效时钟频率的装置和方法。 该装置包括具有至少一个具有逻辑的核心的微处理器，其配置成在状态之间转换，耦合到微处理器的时钟信号，时钟信号具有基于最坏情况时钟频率和预定时钟周期的预定时钟频率。 所述装置还包括耦合到所述芯的至少一个电压降传感器，所述传感器被配置为产生用于检测所述磁芯中的电压降的输出信号，并且确定在所述时钟周期内是否检测到所述输出信号，以及如果 输出信号未检测到，传感器动态地调整提供给核心的时钟信号的时钟周期，以允许更多的时间完成状态转换，使得动态调整时钟周期有效地改变有效的核心时钟频率。

公开(公告)号：US07939910B2

公开(公告)日：2011-05-10

申请号：US12851814

申请日：2010-08-06

申请人： Choongyeun Cho ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

发明人： Choongyeun Cho ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

IPC分类号： H01L29/00

CPC分类号： H01L29/94 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.

摘要翻译： 提供电容电路，其设置在平面前端半导体基底基板上方的下垂直电容器金属层，与底板间隔开的底板距离的平面金属底板和位于底板上方的顶板，间隔开顶板 距离限定金属 - 绝缘体 - 金属电容器的基底的距离，设置在基底基板之上的顶板印迹小于底板印迹并且暴露底板剩余的上横向连接器表面; 将平行的正端口和负端口上垂直电容器金属层布置在每个顶板和底板的上部剩余侧面连接器表面上。 此外，第一顶板和第二底板与正端口金属层以及第二顶板和第一底部到负极金属层的电连接赋予相等的总负端口和正端口金属 - 绝缘体 - 金属电容器 外在电容。

公开(公告)号：US07853808B2

公开(公告)日：2010-12-14

申请号：US11624333

申请日：2007-01-18

申请人： Dae Ik Kim ,  Jonghae Kim ,  Moon J Kim ,  James R Moulic

发明人： Dae Ik Kim ,  Jonghae Kim ,  Moon J Kim ,  James R Moulic

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.

摘要翻译： 提供了系统，方法和程序代码，用于通过控制每个核心的单个电源来选择性地调整多核处理器核心电源电压的多核处理器芯片结构，以确保一个或多个内核按照一个时钟速率运行 或更多性能规格。 标称电源电压被提供给第一处理核心，并且大于或低于标称电源电压的第二核心电源电压被提供给第二处理核心，两个核心都遵守参考时钟速率规范。 第二电源电压可以从通过逐渐降低标称电源电压而导出的有序的离散电源电压中选择，可选地，其中所选择的电源电压还使得第二磁芯能够在另一性能规范内操作。

公开(公告)号：US07816197B2

公开(公告)日：2010-10-19

申请号：US12437575

申请日：2009-05-08

申请人： Jonghae Kim ,  Moon J. Kim ,  Jean-Oliver Plouchart ,  Robert E. Trzcinski

发明人： Jonghae Kim ,  Moon J. Kim ,  Jean-Oliver Plouchart ,  Robert E. Trzcinski

IPC分类号： H01L29/94

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0808 ,  H01L2924/0002 ,  H01L2924/00

摘要： One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.

摘要翻译： 一个或多个片上VNCAP或MIMCAP电容器利用可变MOS电容来改善电容器的均匀电容值。 这允许生产硅半导体芯片，其上安装有具有精确调节的电容值的电容器在其设计值的约1％至5％的范围内。 该优化可以通过使用一对用于DC去耦的可变MOS电容器之间的背对背连接来实现。 它涉及VOCAP和/或MIMCAP电容器的片上BEOL电容的并联，通过在FEOL中插入成对的背对背可变MOS电容器。

公开(公告)号：US07791160B2

公开(公告)日：2010-09-07

申请号：US11923919

申请日：2007-10-25

申请人： Jonghae Kim ,  Sungjae Lee ,  Jean-Olivier Plouchart ,  Scott Keith Springer

发明人： Jonghae Kim ,  Sungjae Lee ,  Jean-Olivier Plouchart ,  Scott Keith Springer

IPC分类号： H01L29/786

CPC分类号： H01L27/0207 ,  H01L21/84 ,  H01L29/4238

摘要： A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.

摘要翻译： 一种用于设计快速FET的快速FET，方法和系统以及快速FET的设计结构。 该方法包括：选择场效应晶体管的参考设计，场效应晶体管包括源极，漏极，源极和漏极之间的沟道，沟道上的栅电极，至少一个源极和源极 所述至少一个源极接触件与所述栅电极隔开第一距离，所述至少一个漏极接触件与所述栅电极间隔开第二距离; 并且调整第一距离和第二距离以最大化场效应晶体管的性能参数以产生用于场效应晶体管的快速设计。