-
公开(公告)号：US20120223411A1
公开(公告)日：2012-09-06
申请号：US13469464
申请日：2012-05-11
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。
-
公开(公告)号：US08227891B2
公开(公告)日：2012-07-24
申请号：US12362877
申请日：2009-01-30
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L21/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。
-
公开(公告)号：US07504705B2
公开(公告)日：2009-03-17
申请号：US11536896
申请日：2006-09-29
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： G06F17/50
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。
-
公开(公告)号：US20100295156A1
公开(公告)日：2010-11-25
申请号：US12851814
申请日：2010-08-06
IPC分类号： H01L29/92
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.
摘要翻译： 提供电容电路，其设置在平面前端半导体基底基板上方的下垂直电容器金属层，与底板间隔开的底板距离的平面金属底板和位于底板上方的顶板，间隔开顶板 距离限定金属 - 绝缘体 - 金属电容器的基底的距离，设置在基底基板之上的顶板印迹小于底板印迹并且暴露底板剩余的上横向连接器表面; 将平行的正端口和负端口上垂直电容器金属层布置在每个顶板和底板的上部剩余侧面连接器表面上。 此外，第一顶板和第二底板与正端口金属层以及第二顶板和第一底部到负极金属层的电连接赋予相等的总负端口和正端口金属 - 绝缘体 - 金属电容器 外在电容。
-
公开(公告)号：US07838384B2
公开(公告)日：2010-11-23
申请号：US11970665
申请日：2008-01-08
IPC分类号： H01L21/20
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Methods, articles and design structures for capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.
摘要翻译： 提供了用于电容电路的方法，制品和设计结构，其在平面前端半导体基底基板上方设置较低的垂直电容器金属层，平板金属底板与底座和顶板间隔开底板 底板与限定金属 - 绝缘体 - 金属电容器的基板间隔开顶板距离，顶板脚印设置在基底基板之上，小于底板印迹，并露出底板剩余的上横向连接器表面; 将平行的正端口和负端口上垂直电容器金属层布置在每个顶板和底板的上部剩余侧面连接器表面上。 此外，第一顶板和第二底板与正端口金属层以及第二顶板和第一底部到负极金属层的电连接赋予相等的总负端口和正端口金属 - 绝缘体 - 金属电容器 外在电容。
-
公开(公告)号：US20090132082A1
公开(公告)日：2009-05-21
申请号：US12362877
申请日：2009-01-30
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。
-
公开(公告)号：US20080079114A1
公开(公告)日：2008-04-03
申请号：US11536896
申请日：2006-09-29
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。
-
公开(公告)号：US08937355B2
公开(公告)日：2015-01-20
申请号：US13469464
申请日：2012-05-11
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L21/00 , H01L49/02 , H01L23/522 , H01L27/02 , H01F17/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
-
公开(公告)号：US07939910B2
公开(公告)日：2011-05-10
申请号：US12851814
申请日：2010-08-06
IPC分类号： H01L29/00
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.
摘要翻译： 提供电容电路，其设置在平面前端半导体基底基板上方的下垂直电容器金属层，与底板间隔开的底板距离的平面金属底板和位于底板上方的顶板，间隔开顶板 距离限定金属 - 绝缘体 - 金属电容器的基底的距离，设置在基底基板之上的顶板印迹小于底板印迹并且暴露底板剩余的上横向连接器表面; 将平行的正端口和负端口上垂直电容器金属层布置在每个顶板和底板的上部剩余侧面连接器表面上。 此外，第一顶板和第二底板与正端口金属层以及第二顶板和第一底部到负极金属层的电连接赋予相等的总负端口和正端口金属 - 绝缘体 - 金属电容器 外在电容。
-
公开(公告)号：US07859825B2
公开(公告)日：2010-12-28
申请号：US12371756
申请日：2009-02-16
IPC分类号： H01G4/38 , H01G4/00 , H01L27/108 , H01L29/94
CPC分类号： H01L27/0811 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.
摘要翻译： 设置安装在半导体芯片上的电容电路组件及其形成方法。 多个发散电容器设置在第一和第二端口之间的并联电路连接中，多个提供至少一个金属氧化物硅电容器和至少一个垂直本机电容器或金属绝缘体金属电容器。 组件具有垂直取向，金属氧化物硅电容器位于底部并限定占地面积，中间垂直本机电容器具有多个水平金属层，包括多个平行的正极板，与多个平行的负极板交替 。 在另一方面，垂直不对称取向提供减小的总寄生电容。
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.036 秒)
