公开(公告)号：US20100259989A1

公开(公告)日：2010-10-14

申请号：US12822584

申请日：2010-06-24

申请人： Jeffrey W. Lutze ,  Dana Lee

发明人： Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C16/04

CPC分类号： H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11568 ,  H01L27/1157

摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

公开(公告)号：US07796430B2

公开(公告)日：2010-09-14

申请号：US12211348

申请日：2008-09-16

申请人： Jeffrey W. Lutze ,  Yingda Dong

发明人： Jeffrey W. Lutze ,  Yingda Dong

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

摘要翻译： 一种减少程序干扰的非易失性存储系统。 在编程非易失性存储时实现多种升压模式。 例如，可以使用自我增强，局部自我增强，消除区域自增强和修改的擦除区域自增强。 使用一个或多个切换标准来确定何时切换到不同的升压模式。 当存储元件被编程在所选择的NAND串中时，升压模式可用于防止未选择的NAND串中的程序干扰。 通过切换升压模式，可以在条件变化时使用最佳升压模式。 可以基于各种标准来切换升压模式，例如程序脉冲数，程序脉冲幅度，程序通过次数，所选字线的位置，是使用粗调还是精细编程，存储元件是否达到程序状态和/ 或非易失性存储设备的多个程序周期。

公开(公告)号：US20100097861A1

公开(公告)日：2010-04-22

申请号：US12252727

申请日：2008-10-16

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5648

摘要： A multiple pass programming scheme is optimized using capacitive coupling in the word line to word line direction during program-verify operations. A different pass voltage is used in different programming passes on an adjacent word line of a selected word line which is being verified. In particular, a lower pass voltage can be used in a first pass than in a second pass. The programming process may involve a word line look ahead or zigzag sequence in which WLn is programmed in a first pass, followed by WLn+1 in a first pass, followed by WLn in a second pass, followed by WLn+1 in a second pass. An initial programming pass may be performed before the first pass in which storage elements are programmed to an intermediate state and/or to a highest state.

摘要翻译： 在编程验证操作期间，使用字线到字线方向的电容耦合来优化多通道编程方案。 在正在验证的所选择的字线的相邻字线上的不同的编程遍中使用不同的通过电压。 特别地，可以在第一遍中比在第二遍中使用较低通过电压。 编程过程可以包括字线前视或之字形序列，其中WLn在第一遍中编程，其次是第一遍中的WLn + 1，之后是第二遍中的WLn，之后是第二遍中的WLn + 1 。 可以在其中存储元件被编程到中间状态和/或最高状态的第一遍之前执行初始编程遍。

公开(公告)号：US20100034022A1

公开(公告)日：2010-02-11

申请号：US12188629

申请日：2008-08-08

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418

摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

摘要翻译： 通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。 执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压 字线。 当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。 也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据 相邻的存储元件。

公开(公告)号：US07623387B2

公开(公告)日：2009-11-24

申请号：US11609813

申请日：2006-12-12

申请人： Yingda Dong ,  Jeffrey W. Lutze

发明人： Yingda Dong ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

摘要： Non-volatile storage with reduced program disturb is provided by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a first boost mode is used when the selected word line is a lower or intermediate word line. In the first boost mode, boosting of the source and drain side channels is initiated concurrently. A second boost mode is used when the selected word line is a higher word line. In the second boost mode, boosting of the source side channel occurs early relative to the boosting of the drain side channel. Either boost mode include an isolation voltage which tends to isolate the source and drain side channels from one another.

摘要翻译： 通过将阵列中未选择的NAND串升压来提供具有减少的编程干扰的非易失性存储器，使得在所选择的字线的源极侧上的源极通道在所选择的漏极侧的漏极侧之前被提升在漏极侧通道之前 字线。 在一种方法中，当所选字线是较低或中间字线时，使用第一升压模式。 在第一升压模式中，同时启动源极和漏极侧通道的升压。 当所选字线是较高字线时，使用第二升压模式。 在第二升压模式中，源极侧沟道的升压相对于漏极侧沟道的升压而早期发生。 升压模式包括易于将源极和漏极侧通道彼此隔离的隔离电压。

公开(公告)号：US07468918B2

公开(公告)日：2008-12-23

申请号：US11618594

申请日：2006-12-29

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee ,  Gerrit Jan Hemink

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.

摘要翻译： 在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。 在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。 在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

公开(公告)号：US07468911B2

公开(公告)日：2008-12-23

申请号：US11555856

申请日：2006-11-02

申请人： Jeffrey W. Lutze ,  Yingda Dong

发明人： Jeffrey W. Lutze ,  Yingda Dong

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

摘要翻译： 一种减少程序干扰的非易失性存储系统。 在编程非易失性存储时实现多种升压模式。 例如，可以使用自我增强，局部自我增强，消除区域自增强和修改的擦除区域自增强。 使用一个或多个切换标准来确定何时切换到不同的升压模式。 当存储元件被编程在所选择的NAND串中时，升压模式可用于防止未选择的NAND串中的程序干扰。 通过切换升压模式，可以在条件变化时使用最佳升压模式。 可以基于各种标准来切换升压模式，例如程序脉冲数，程序脉冲幅度，程序通过次数，所选字线的位置，是使用粗调还是精细编程，存储元件是否达到程序状态和/ 或非易失性存储设备的多个程序周期。

公开(公告)号：US07463522B2

公开(公告)日：2008-12-09

申请号：US11745092

申请日：2007-05-07

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

IPC分类号： G11C16/00

CPC分类号： G11C8/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

摘要： Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.

摘要翻译： 通过防止所选择的NAND串中的源极升压来减少编程干扰的非易失性存储。 使用包括隔离字线的自增强模式。 禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。 此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。 以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。 在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

公开(公告)号：US07460406B2

公开(公告)日：2008-12-02

申请号：US12023317

申请日：2008-01-31

申请人： Nima Mokhlesi ,  Jeffrey W. Lutze

发明人： Nima Mokhlesi ,  Jeffrey W. Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/28

摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

公开(公告)号：US20080291735A1

公开(公告)日：2008-11-27

申请号：US11753958

申请日：2007-05-25

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/10

摘要： To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.

摘要翻译： 为了对一个或多个非易失性存储元件进行编程，例如通过公共字线将一组编程脉冲施加到至少一个选定的非易失性存储元件和一个或多个特定未选择的非易失性存储元件。 在编程过程期间将升压电压施加到其它未选择的非易失性存储元件，以便增强未选择的非易失性存储元件的通道，从而禁止编程。 每个编程脉冲具有第一中间幅度，第二中间幅度和第三幅度。 在一个实施例中，第一中间幅度与升压电压相似或相同。 第二中间幅度大于第一中间幅度，但小于第三幅度。 这样的布置可以减少节目干扰的影响。