公开(公告)号：US07868542B2

公开(公告)日：2011-01-11

申请号：US12028107

申请日：2008-02-08

申请人： Koichi Fukuda

发明人： Koichi Fukuda

IPC分类号： H05B33/02 ,  H05B33/00 ,  H01L33/00

CPC分类号： H01L51/5262 ,  H01L27/3246 ,  H01L33/44 ,  H01L33/54 ,  H01L51/0081 ,  H01L51/0085 ,  H01L51/5265 ,  H01L51/5268 ,  H01L2251/5315

摘要： Provided is a light-emitting apparatus which can improve the light extraction efficiency without adversely influencing a functional layer of a light-emitting device and which includes a substrate; a light-emitting device formed on the substrate, the light-emitting device including: a first electrode formed on the substrate; an insulating member covering a periphery of the first electrode; and a functional layer formed on an exposed portion of the first electrode and including an emission layer; and a second electrode formed on the functional layer and the insulating member, in which a periodic structure is formed on a surface of the insulating member opposite to a substrate side, and an optical waveguide is formed between a bottom portion of the periodic structure and the first electrode or between the bottom portion of the periodic structure and the substrate.

摘要翻译： 提供一种可以提高光提取效率而不会不利地影响发光装置的功能层并且包括基板的发光装置; 形成在所述基板上的发光装置，所述发光装置包括：形成在所述基板上的第一电极; 覆盖所述第一电极的周边的绝缘构件; 以及形成在所述第一电极的暴露部分上并且包括发射层的功能层; 以及形成在功能层和绝缘构件上的第二电极，其中在绝缘构件的与衬底侧相对的表面上形成周期性结构，并且在周期结构的底部和 第一电极或在周期性结构的底部和基板之间。

公开(公告)号：US20100084702A1

公开(公告)日：2010-04-08

申请号：US12564615

申请日：2009-09-22

申请人： Koichi Fukuda ,  Rieko Tanaka ,  Takumi Abe

发明人： Koichi Fukuda ,  Rieko Tanaka ,  Takumi Abe

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11531 ,  H01L27/105 ,  H01L27/11526 ,  H01L28/24

摘要： A nonvolatile semiconductor memory device comprises a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer. The second semiconductor layer is formed to extend in a first direction parallel to the substrate. The second low resistive layer is formed at both ends of the second semiconductor layer in the first direction.

摘要翻译： 非易失性半导体存储器件包括被配置为存储数据的存储单元和设置在存储单元周围的电阻元件。 存储单元包括设置在基板上的电荷存储层，经由绝缘层形成在电荷存储层的顶表面上的第一半导体层和形成在第一半导体层的顶表面上的第一低电阻层，并且具有 电阻低于第一半导体层的电阻。 电阻元件包括形成在与第一半导体层相同的层上的第二半导体层，以及形成在与第一低电阻层相同的层上的第二低电阻层，以及形成在第二半导体层的顶表面上的第二低电阻层， 比第二半导体层的厚度大。 第二半导体层形成为在与基板平行的第一方向上延伸。 第二低电阻层在第一方向上形成在第二半导体层的两端。

公开(公告)号：US07652928B2

公开(公告)日：2010-01-26

申请号：US11778220

申请日：2007-07-16

申请人： Kosuke Yanagidaira ,  Koichi Fukuda ,  Takahiko Hara

发明人： Kosuke Yanagidaira ,  Koichi Fukuda ,  Takahiko Hara

IPC分类号： G11C16/06

CPC分类号： G11C16/349 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3404

摘要： A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter.

摘要翻译： 半导体存储器件包括存储单元阵列，电压产生电路，存储存储单元阵列的提前写入电压的参考脉冲数和参数的存储器电路，以及控制电路，当脉冲数 所述提前写入电压小于所述提前写入电压的参考脉冲数，所述电压产生电路以至少降低写入电压的初始值和写入电压的升压宽度 与参数。

公开(公告)号：US07630261B2

公开(公告)日：2009-12-08

申请号：US11770252

申请日：2007-06-28

申请人： Takumi Abe ,  Hiroshi Maejima ,  Koichi Fukuda ,  Takahiko Hara

发明人： Takumi Abe ,  Hiroshi Maejima ,  Koichi Fukuda ,  Takahiko Hara

IPC分类号： G11C7/02

CPC分类号： G11C11/5621 ,  G11C16/0483 ,  G11C2211/5641

摘要： A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor, a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate, a dummy gate driving circuit controlling a potential of the control gate of the dummy gate, and a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing the external data.

摘要翻译： 一种NAND结构的闪速存储器，包括具有第一导电路径的选择晶体管，第一导电路径的一端连接到位线或源极线，至少一个具有第二导电路径和控制栅极的虚拟栅极，一个 第二导电路径的端部连接到选择晶体管的第一导电路径的另一端，用于存储外部数据的非易失性存储器链接单元，其包括具有第三导电路径和控制的多个电可擦除/可写非易失性存储单元 所述第三导电路径串联连接，所述第三导电路径的一端与所述虚拟栅极的所述第二导电路径的另一端连接，所述虚拟栅极驱动电路控制所述控制栅极的电位 所述虚拟栅极和存储单元驱动电路选择性地驱动所述多个非易失性存储单元的控制栅极进行写入，读取或者错误 e位用于存储外部数据的数据。

公开(公告)号：US20090213306A1

公开(公告)日：2009-08-27

申请号：US12437218

申请日：2009-05-07

申请人： Koichi Fukuda

发明人： Koichi Fukuda

IPC分类号： G02F1/1335 ,  G02F1/1333

CPC分类号： H01L27/124 ,  G02F1/1333 ,  G02F1/133305 ,  G02F1/133308 ,  G02F1/133528 ,  G02F1/133536 ,  G02F1/133608 ,  G02F1/1339 ,  G02F1/1368 ,  G02F2201/50

摘要： A liquid crystal display includes a liquid crystal display panel having a first substrate, a second substrate disposed on an observer side with respect to the first substrate and opposed to the first substrate, a liquid crystal held between the first substrate and the second substrate, an upper polarizing plate disposed on the observer side with respect to the second substrate, and a resin film disposed on the observer side with respect to the upper polarizing plate and affixed in contact with the upper polarizing plate. The resin film is higher in surface hardness than the upper polarizing plate and has a surface hardness of at least 3H in terms of surface pencil hardness. Each of the first and second substrates have a thickness of no greater than 0.5 mm, and a total thickness of the liquid crystal display panel is no greater than 2 mm.

摘要翻译： 液晶显示器包括液晶显示面板，其具有第一基板，相对于第一基板设置在观察者侧并与第一基板相对的第二基板，保持在第一基板和第二基板之间的液晶， 相对于第二基板设置在观察者侧的上偏振片和相对于上偏振片设置在观察者侧并与上偏振片接触的树脂膜。 树脂膜的表面硬度高于上偏振片，表面硬度以表面铅笔硬度计至少为3H。 第一基板和第二基板中的每一个具有不大于0.5mm的厚度，并且液晶显示面板的总厚度不大于2mm。

公开(公告)号：US07514747B2

公开(公告)日：2009-04-07

申请号：US11798988

申请日：2007-05-18

申请人： Koichi Fukuda

发明人： Koichi Fukuda

IPC分类号： H01L23/62

CPC分类号： H01L29/78612 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device formed in a silicon-on-insulator substrate includes a silicon channel region located between silicon source and drain regions, and a low-carrier-concentration layer that underlies the channel region. The low-carrier-concentration layer makes contact with both the channel region and the source region. The channel region and the low-carrier-concentration layer are of the same conductive type, but the low-carrier-concentration layer is doped to have a lower carrier concentration than the channel region. The low-carrier-concentration layer eliminates the floating substrate effect, because carriers that would otherwise accumulate in the channel region can escape through the low-carrier-concentration layer into the source region.

摘要翻译： 形成在绝缘体上硅衬底中的半导体器件包括位于硅源极和漏极区之间的硅沟道区，以及位于沟道区之下的低载流子浓度层。 低载流子浓度层与沟道区域和源极区域接触。 沟道区域和低载流子浓度层具有相同的导电类型，但是低载流子浓度层被掺杂以具有比沟道区域更低的载流子浓度。 低载流子浓度层消除浮置衬底效应，因为否则在沟道区积聚的载流子可以通过低载流子浓度层逸出到源区。

公开(公告)号：US07420853B2

公开(公告)日：2008-09-02

申请号：US11836907

申请日：2007-08-10

申请人： Koichi Fukuda

发明人： Koichi Fukuda

IPC分类号： G11C11/34

CPC分类号： G11C16/30 ,  G11C16/16

摘要： A semiconductor storage device comprises a semiconductor layer; a plurality of memory cells formed on the semiconductor layer, data writing, erasing or reading with respect to each of the memory cells being possible based on a voltage applied to a control electrode and a voltage applied to the semiconductor layer; a first booster circuit supplying a voltage to control electrodes of selected memory cells into which data is to be written; and a second booster circuit supplying a voltage to control electrodes of inhibited memory cells into which data is not to be written, wherein when erasing data in the memory cells, a potential at the semiconductor layer is boosted in a first boosting mode in which a boosting capability of the first booster circuit is low and a boosting capability of the second booster circuit is high, and then the potential at the semiconductor layer is boosted in a second boosting mode in which the boosting capability of the second booster circuit is low and the boosting capability of the first booster circuit is high.

摘要翻译： 半导体存储装置包括半导体层; 基于施加到控制电极的电压和施加到半导体层的电压，形成在半导体层上的多个存储单元，相对于每个存储单元的数据写入，擦除或读取是可能的; 向要写入数据的所选存储单元的控制电极提供电压的第一升压电路; 以及第二升压电路，向要写入数据的禁止存储单元的控制电极提供电压，其中当擦除存储单元中的数据时，在第一升压模式中升压半导体层的电位，其中升压 第一升压电路的能力低，第二升压电路的升压能力高，然后在第二升压电路的升压能力低的升压模式下升压半导体层的电位，并且升压 第一升压电路的能力很高。

公开(公告)号：US07269074B2

公开(公告)日：2007-09-11

申请号：US11368484

申请日：2006-03-07

申请人： Koichi Fukuda

发明人： Koichi Fukuda

IPC分类号： G11C11/34

CPC分类号： G11C16/30 ,  G11C16/16

摘要： A semiconductor storage device comprises a semiconductor layer; a plurality of memory cells formed on the semiconductor layer, data writing, erasing or reading with respect to each of the memory cells being possible based on a voltage applied to a control electrode and a voltage applied to the semiconductor layer; a first booster circuit supplying a voltage to control electrodes of selected memory cells into which data is to be written; and a second booster circuit supplying a voltage to control electrodes of inhibited memory cells into which data is not to be written, wherein when erasing data in the memory cells, a potential at the semiconductor layer is boosted in a first boosting mode in which a boosting capability of the first booster circuit is low and a boosting capability of the second booster circuit is high, and then the potential at the semiconductor layer is boosted in a second boosting mode in which the boosting capability of the second booster circuit is low and the boosting capability of the first booster circuit is high.

摘要翻译： 半导体存储装置包括半导体层; 基于施加到控制电极的电压和施加到半导体层的电压，形成在半导体层上的多个存储单元，相对于每个存储单元的数据写入，擦除或读取是可能的; 向要写入数据的所选存储单元的控制电极提供电压的第一升压电路; 以及第二升压电路，向要写入数据的禁止存储单元的控制电极提供电压，其中当擦除存储单元中的数据时，在第一升压模式中升压半导体层的电位，其中升压 第一升压电路的能力低，第二升压电路的升压能力高，然后在第二升压电路的升压能力低的升压模式下升压半导体层的电位，并且升压 第一升压电路的能力很高。

公开(公告)号：US07224608B2

公开(公告)日：2007-05-29

申请号：US11246164

申请日：2005-10-11

申请人： Koichi Fukuda

发明人： Koichi Fukuda

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/0483

摘要： A semiconductor device includes an electrical circuit formed on a substrate; a level detector outputting a first level signal which has a signal level based on power supply voltage and which determines an operation of the electrical circuit; a command decoder decoding a command that is inputted from the outside, and outputting a command signal; a control circuit to which the command signal is inputted, the control circuit outputting a state signal expressing whether the electrical circuit is in an operation state; and a first latch circuit to which the first level signal and the state signal are inputted, the first latch circuit latching the first level signal at a time based on the state signal.

摘要翻译： 半导体器件包括形成在衬底上的电路; 电平检测器输出基于电源电压具有信号电平的第一电平信号，并且确定电路的操作; 解码从外部输入的命令并输出命令信号的命令解码器; 输入指令信号的控制电路，所述控制电路输出表示所述电路是否处于工作状态的状态信号; 以及第一锁存电路，第一电平信号和状态信号被输入到其中，第一锁存电路基于状态信号一次锁存第一电平信号。

公开(公告)号：US07199000B2

公开(公告)日：2007-04-03

申请号：US10875683

申请日：2004-06-25

申请人： Koichi Fukuda

发明人： Koichi Fukuda

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： Several a transistor, which are inhibited short channel effect moderately according to each transistor's channel length, are formed on a same SOI substrate.In the present invention, forming a first transistor on SOI substrate, and forming a second transistor which has a gate electrode whose length is longer than a gate length of the first transistor in a channel directionThe impurities are doped from above a surface of the SOI substrate in an oblique direction against the surface, and from source side and drain side of the first transistor and the second transistor.By this means, a pocket layer is formed under an insulator layer of a SOI substrate.

摘要翻译： 根据每个晶体管的沟道长度抑制短沟道效应的几个晶体管形成在同一SOI衬底上。