公开(公告)号：US06580075B2

公开(公告)日：2003-06-17

申请号：US10251749

申请日：2002-09-23

申请人： Masatsugu Kametani ,  Kenjiro Yamamoto ,  Taku Ninomiya ,  Osamu Yamada ,  Katsuhisa Ike

发明人： Masatsugu Kametani ,  Kenjiro Yamamoto ,  Taku Ninomiya ,  Osamu Yamada ,  Katsuhisa Ike

IPC分类号： G01N2300

CPC分类号： H01J37/28 ,  H01J2237/2817

摘要： A charged particle beam scanning inspecting apparatus for irradiating a charged particle beam, fetching information of a subject to be inspected at a predetermined beam scanning position and performing an inspection by processing the information. The apparatus is a measurer which measures a scanning position of the beam and an inspection position on said inspection subject to calculate beam target coordinates corrected for an apparatus error, an error correction constant and a deflected distortion correction constant, and a deflection controller for scanning the beam. The deflection controller includes a deflection position operating circuit for performing an operation of the inspection position in a deflection coordinate system, a deflected distortion operating circuit. The deflection position operating circuit and deflected distortion operating circuit are constructed in a pipe line fashion.

摘要翻译： 一种用于照射带电粒子束的带电粒子束扫描检查装置，在预定的束扫描位置获取要检查的对象的信息，并通过处理该信息进行检查。 该装置是测量光束的扫描位置和所述检查对象上的检查位置的计量器，用于计算针对装置误差校正的光束目标坐标，误差校正常数和偏转失真校正常数，以及用于扫描 光束。 偏转控制器包括用于在偏转坐标系中执行检查位置的操作的偏转位置操作电路，偏转失真操作电路。 偏转位置操作电路和偏转失真操作电路以管道方式构成。

公开(公告)号：US06468441B1

公开(公告)日：2002-10-22

申请号：US09795133

申请日：2001-03-01

申请人： Osamu Kobayashi ,  Osamu Yamada ,  Kiyoshi Ito

发明人： Osamu Kobayashi ,  Osamu Yamada ,  Kiyoshi Ito

IPC分类号： C04B3526

CPC分类号： C04B35/2658 ,  C04B35/265

摘要： The present invention provides a Mn—Zn ferrite having an electrical resistivity exceeding 1 &OHgr;m order and a low core loss in a high frequency region exceeding 1 MHz. A basic component composition of the Mn—Zn ferrite includes 44.0 to 49.8 mol % of Fe2O3, 6.0 to 15.0 mol % of ZnO (15.0 mol % is excluded), 0.1 to 3.0 mol % of CoO, 0.02 to 1.20 mol % of Mn2O3, and the remainder of MnO. The Mn—Zn ferrite achieves desired purposes by controlling Fe2O3 content to a range less than 50 mol % that is the stoichiometric composition, adding a proper amount of CoO, restraining amount of Mn2O3 formation to 1.20 mol % or less, and further setting their average grain sizes to less than 10 &mgr;m.

摘要翻译： 本发明提供一种电阻率超过1欧姆等级的Mn-Zn铁氧体，超高于1MHz的高频区域的低铁损。 Mn-Zn铁氧体的基本成分组成包括Fe2O3为44.0〜49.8mol％，ZnO为6.0〜15.0mol％（不包括15.0mol％），CoO为0.1〜3.0mol％，Mn2O3为0.02〜1.20mol％ 和剩余的MnO。 Mn-Zn铁氧体通过将Fe 2 O 3含量控制在化学计量组成小于50摩尔％的范围内，添加适量的CoO，抑制Mn2O3的形成量为1.20摩尔％以下，进一步设定其平均值 粒径小于10um。

公开(公告)号：US06461531B2

公开(公告)日：2002-10-08

申请号：US09795116

申请日：2001-03-01

申请人： Osamu Kobayashi ,  Osamu Yamada ,  Kiyoshi Ito

发明人： Osamu Kobayashi ,  Osamu Yamada ,  Kiyoshi Ito

IPC分类号： C04B3526

CPC分类号： C04B35/2658

摘要： The present invention provides a Mn—Zn ferrite having an electrical resistivity exceeding 1 &OHgr;m order and having a low core loss in a high frequency region exceeding 1 MHz. The basic component composition of the Mn—Zn ferrite includes 44.0 to 49.8 mol % Fe2O3, 6.0 to 15.0 mol % ZnO (15.0 mol % is excluded), 0.1 to 4.0 mol % at least one of TiO2 and SnO2, and remainder MnO, wherein desired results are obtained by limiting Fe2O3 content to less than 50 mol % that is the stoichiometric composition and adding a proper amount of TiO2 or SnO2 and further controlling its average grain size to less than 10 &mgr;m.

摘要翻译： 本发明提供一种具有超过1欧姆等级的电阻率并且在超过1MHz的高频区域具有低铁损的Mn-Zn铁氧体。 Mn-Zn系铁氧体的基本成分组成包括Fe2O3为44.0〜49.8mol％，ZnO为6.0〜15.0mol％（不包括15.0mol％），TiO 2和SnO 2中的至少一种为0.1〜4.0mol％，余量为MnO，其中， 通过将Fe 2 O 3含量限制为小于化学计量组成的50mol％并加入适量的TiO 2或SnO 2并进一步控制其平均晶粒尺寸小于10um而得到期望的结果。

公开(公告)号：US6094738A

公开(公告)日：2000-07-25

申请号：US121954

申请日：1998-07-24

申请人： Osamu Yamada ,  Koji Hara

发明人： Osamu Yamada ,  Koji Hara

IPC分类号： G01R31/28

CPC分类号： G01R31/28

摘要： A test pattern generation apparatus and method for an SDRAM can easily generate a test pattern for a synchronous dynamic RAM (SDRAM) by having a specific wrap conversion circuit or an address conversion method. The wrap conversion circuit is provided to receive two types of address data from a pattern generator and converts the data through a specified logic circuit information. The test pattern generation method for the SDRAM is carried out by inputting column address data and wrap address data, and by generating output data which has been converted by a predetermined logic equation. The test pattern generation apparatus and method can also include an address inversion scramble for the converted output.

摘要翻译： 用于SDRAM的测试图形生成装置和方法可以通过具有特定的卷绕转换电路或地址转换方法来容易地生成用于同步动态RAM（SDRAM）的测试模式。 提供包裹转换电路以从模式发生器接收两种类型的地址数据，并通过指定的逻辑电路信息转换数据。 通过输入列地址数据和包裹地址数据，并且通过产生已经通过预定逻辑等式转换的输出数据来执行用于SDRAM的测试图案生成方法。 测试模式生成装置和方法还可以包括用于转换的输出的地址反向加扰。

公开(公告)号：US5958768A

公开(公告)日：1999-09-28

申请号：US697324

申请日：1996-08-23

申请人： Gunter Kraus ,  Flossie Wong-Staal ,  Mang Yu ,  Osamu Yamada

发明人： Gunter Kraus ,  Flossie Wong-Staal ,  Mang Yu ,  Osamu Yamada

IPC分类号： A61K38/00 ,  A61K48/00 ,  C07K14/47 ,  C12N15/113 ,  C07H21/04 ,  C12N5/16 ,  C12N5/22 ,  C12N15/79 ,  C12N15/85

CPC分类号： C12N15/1132 ,  C07K14/4705 ,  A61K38/00 ,  A61K48/00 ,  C07K2319/00 ,  C12N2310/111 ,  C12N2310/121 ,  C12N2310/13

摘要： Methods and compositions for the treatment and diagnosis of infections of Rev-binding primate lentiviruses are provided. These methods and compositions utilize the ability of Rev binding nucleic acids such as the SLII sequence from the HIV-1 Rev response element (RRE) to target therapeutic agents to the same sub-cellular location as primate lentiviruses which contain RRE sequences. In particular, the invention provides trans-acting ribozymes comprising Rev-binding nucleic acids less toxic than a full-length RRE, and molecules encoding them. The use of the compositions of the invention as components of diagnostic assays, as prophylactic reagents, and in vectors is also described.

摘要翻译： 提供了用于治疗和诊断Rev-binding灵长类慢病毒感染的方法和组合物。 这些方法和组合物利用Rev结合核酸如来自HIV-1 Rev反应元件（RRE）的SLII序列的能力将治疗剂靶向与含有RRE序列的灵长类慢病毒相同的亚细胞位置。 特别地，本发明提供了包含与全长RRE相比毒性小的Rev结合核酸的反式作用核酶以及编码它们的分子。 还描述了将本发明的组合物用作诊断测定的组分作为预防试剂和载体的用途。

公开(公告)号：US5956421A

公开(公告)日：1999-09-21

申请号：US807605

申请日：1997-02-27

申请人： Tetsuomi Tanaka ,  Osamu Yamada

发明人： Tetsuomi Tanaka ,  Osamu Yamada

IPC分类号： G06K9/38 ,  G06T5/00 ,  G06T5/40

CPC分类号： G06K9/38 ,  G06T7/0081 ,  H04N1/403 ,  G06K2209/01 ,  G06T2207/20148 ,  G06T2207/30176

摘要： An image processor determines a binarization threshold value used for binarizing a multi-valued image, and performs binarization processing on the multi-valued image. The multi-valued image is input line-sequentially, the binarization threshold values are determined sequentially in units of predetermined size blocks each including a plurality of pixels, and the multi-valued image data is binarized line-sequentially. The inputting of data, determining the threshold value, and binarization of the multi-value image data is performed by pipeline processing.

摘要翻译： 图像处理器确定用于二值化多值图像的二值化阈值，并对多值图像执行二值化处理。 多值图像是按顺序输入的，以包含多个像素的预定大小的块为单位确定二值化阈值，并且多值图像数据被逐行二进制化。 通过流水线处理来执行数据的输入，确定阈值和多值图像数据的二值化。

公开(公告)号：US5788385A

公开(公告)日：1998-08-04

申请号：US901956

申请日：1997-07-29

申请人： Naoshi Inoue ,  Kiyoharu Yoshioka ,  Hiroyuki Kuriyama ,  Soji Hamano ,  Akihiko Hamamoto ,  Makoto Hinohara ,  Osamu Yamada

发明人： Naoshi Inoue ,  Kiyoharu Yoshioka ,  Hiroyuki Kuriyama ,  Soji Hamano ,  Akihiko Hamamoto ,  Makoto Hinohara ,  Osamu Yamada

IPC分类号： B41J2/505 ,  G06K15/10 ,  B41J19/00

CPC分类号： B41J19/202 ,  B41J2/5056 ,  G06K15/10 ,  G06K2215/0071

摘要： A recording apparatus for recording an image on a recording medium by scanning a recording head, includes a scan unit for scanning the recording head by changing the scan speed of the recording head, and a control unit for controlling the scan unit to change the scan speed of the recording head according to the resolution of image data to be recorded by the recording head so as to perform recording. A recording controller for controlling the recording apparatus is also disclosed.

摘要翻译： 一种用于通过扫描记录头将图像记录在记录介质上的记录装置，包括：扫描单元，用于通过改变记录头的扫描速度扫描记录头;以及控制单元，用于控制扫描单元改变扫描速度 根据由记录头记录的图像数据的分辨率来进行记录。 还公开了一种用于控制记录装置的记录控制器。

公开(公告)号：US5432800A

公开(公告)日：1995-07-11

申请号：US968406

申请日：1992-10-29

申请人： Toru Kuroda ,  Masafumi Saito ,  Shigeki Moriyama ,  Tomohiro Saito ,  Masayuki Takada ,  Osamu Yamada

发明人： Toru Kuroda ,  Masafumi Saito ,  Shigeki Moriyama ,  Tomohiro Saito ,  Masayuki Takada ,  Osamu Yamada

IPC分类号： H03M13/29 ,  H03M13/33 ,  H04L1/00 ,  H04L7/10 ,  G06F11/10

CPC分类号： H03M13/29 ,  H03M13/33 ,  H04L1/0083 ,  H04L7/10 ,  H04H2201/15

摘要： Method and apparatus for transmitting an information signal generate a plurality of block signals on the basis of the information signal, generate a plurality of parity block signals on the basis of the plural data block signals, generate a frame signal containing the plural data block signals and the parity block signals, and send out the frame signal. Each of the data block signals includes a first block synchronizing signal indicating the start of the data block signal, a data signal containing the information signal and a first parity signal derived by encoding the data signal. Each of the parity block signals incudes a second block synchronizing signal indicating the start of the parity block signal, a second parity signal and a third parity signal. Bit signals located at same bit positions in the respective second parity signals are derived by encoding bit signals located at the same positions in the respective data signals. Bit signals located at same bit positions in the respective third parity signals are derived by encoding the bit signals located at the same bit positions in the respective first parity signals or alternatively the third parity signal in each parity block signal is derived by encoding the second parity signal in each parity block signal.

摘要翻译： 用于发送信息信号的方法和装置基于信息信号产生多个块信号，根据多个数据块信号产生多个奇偶校验块信号，生成包含多个数据块信号的帧信号，以及 奇偶校验块信号，并发出帧信号。 每个数据块信号包括指示数据块信号的开始的第一块同步信号，包含信息信号的数据信号和通过对数据信号进行编码导出的第一奇偶校验信号。 每个奇偶校验块信号包括指示奇偶校验块信号的开始的第二块同步信号，第二奇偶校验信号和第三奇偶校验信号。 通过对位于相应数据信号中的相同位置的位信号进行编码，导出位于各个第二奇偶校验信号中相同位位置的位信号。 通过对位于相应的第一奇偶校验信号中的相同位位置的位信号进行编码，或者通过对第二奇偶校验位进行编码来导出每个奇偶校验块信号中的第三奇偶校验信号，导出位于相应的第三奇偶校验信号中位于相同位位置的位信号 信号在每个奇偶校验块信号。

公开(公告)号：US5296680A

公开(公告)日：1994-03-22

申请号：US21558

申请日：1993-02-24

申请人： Osamu Yamada

发明人： Osamu Yamada

IPC分类号： B23K1/008 ,  B23K31/02 ,  H05K3/34 ,  H05K13/00 ,  H05K13/04 ,  B23K3/04

CPC分类号： B23K1/008 ,  H05K13/0061 ,  H05K13/0465 ,  B23K2201/40

摘要： An automatic soldering apparatus for soldering a printed circuit board includes a plurality of electronic elements mounted thereon to be soldered thereto. The apparatus is structured to have a first station provided with a first outer opening for enabling the printed circuit board to be transported therethrough into a heating chamber so as to be soldered therein and further provided with a first inner opening, a second station provided with a second outer opening for enabling the soldered printed circuit board to be transported therethrough out of the heating chamber, and further provided with a second inner opening, and a duct having one end opening and an opposite end opening, the one end opening being connected to the first inner opening of the first station and the opposite end opening being connected to the second inner opening of the second station, the areas of the first inner opening the one end opening being larger than the area of the first outer opening, and the areas of the second inner opening and the opposite end opening being larger than the area of the second outer opening.

摘要翻译： 用于焊接印刷电路板的自动焊接装置包括安装在其上待焊接的多个电子元件。 该设备被构造成具有设置有第一外部开口的第一站，用于使印刷电路板能够通过其传送到加热室中，以便被焊接在其中并且还设置有第一内部开口，第二站设置有 第二外部开口，用于使焊接的印刷电路板能够从加热室输送出去，并且还设置有第二内部开口和具有一个端部开口和相对端部开口的管道，该一个端部开口连接到 第一站的第一内开口和与第二站的第二内开口连接的相对端开口，第一内开口的一端开口面积大于第一外开口的面积， 第二内开口和相对端开口大于第二外开口的面积。

公开(公告)号：US5003540A

公开(公告)日：1991-03-26

申请号：US238838

申请日：1988-08-31

申请人： Koichi Yamazaki ,  Yasuyuki Kimura ,  Osamu Yamada ,  Toru Kuroda

发明人： Koichi Yamazaki ,  Yasuyuki Kimura ,  Osamu Yamada ,  Toru Kuroda

IPC分类号： H04L1/00 ,  H03M13/00 ,  H03M13/33 ,  H03M13/43

CPC分类号： H03M13/33 ,  H03M13/43

摘要： An error correction coding and decoding circuit for digitally coded information in which a majority difference set cyclic code is used to apply error correction coding and decoding to a data signal having data bits suitably assigned to information bits and parity bits, characterized in that a clock signal (CLKC) for the internal operation of the circuit, a data load clock signal for loading data onto the circuit, and a data read clock signal for reading data from the circuit are delivered from an external circuit provided separately from the error correction coding and decoding circuit.