Method and structure for a 1T-RAM bit cell and macro
    81.
    发明申请
    Method and structure for a 1T-RAM bit cell and macro 有权
    1T-RAM位元和宏的方法和结构

    公开(公告)号:US20070080387A1

    公开(公告)日:2007-04-12

    申请号:US11246318

    申请日:2005-10-07

    IPC分类号: H01L27/108

    摘要: A one transistor (1T-RAM) bit cell and method for manufacture are provided. A metal-insulator-metal (MIM) capacitor structure and method of manufacturing it in an integrated process that includes a finFET transistor for the 1T-RAM bit cell is provided. In some embodiments, the finFET transistor and MIM capacitor are formed in a memory region and an asymmetric processing method is disclosed, which allows planar MOSFET transistors to be formed in another region of a single device. In some embodiments, the 1T-RAM cell and additional transistors may be combined to form a macro cell, multiple macro cells may form an integrated circuit. The MIM capacitors may include nanoparticles or nanostructures to increase the effective capacitance. The finFET transistors may be formed over an insulator. The MIM capacitors may be formed in interlevel insulator layers above the substrate. The process provided to manufacture the structure may advantageously use conventional photomasks.

    摘要翻译: 提供一个晶体管(1T-RAM)位单元及其制造方法。 提供了一种金属 - 绝缘体金属(MIM)电容器结构及其制造方法,其集成工艺包括用于1T-RAM位元的finFET晶体管。 在一些实施例中,finFET晶体管和MIM电容器形成在存储区域中,并且公开了一种不对称处理方法,其允许在单个器件的另一个区域中形成平面MOSFET晶体管。 在一些实施例中,可以组合1T-RAM单元和附加晶体管以形成宏小区,多个宏小区可以形成集成电路。 MIM电容器可以包括纳米颗粒或纳米结构以增加有效电容。 finFET晶体管可以形成在绝缘体上。 MIM电容器可以形成在衬底上方的层间绝缘体层中。 提供用于制造结构的方法可以有利地使用常规的光掩模。

    Semiconductor structure and method for integrating SOI devices and bulk devices
    82.
    发明授权
    Semiconductor structure and method for integrating SOI devices and bulk devices 有权
    用于集成SOI器件和散装器件的半导体结构和方法

    公开(公告)号:US07105897B2

    公开(公告)日:2006-09-12

    申请号:US10977236

    申请日:2004-10-28

    摘要: This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.

    摘要翻译: 本发明公开了一种用于集成至少一个体器件和至少一个绝缘体上硅(SOI)器件的方法和半导体结构。 半导体结构包括具有SOI区域和体积区域的第一基板,在其上形成散装器件; 形成在SOI区域的第一基板上的绝缘层; 以及在其上形成有SOI器件的第二衬底,堆叠在绝缘层上。 第一基板的表面不在与第二基板的表面基本相同的平面上。

    File folder, box and panel designed with pre-perforated holes, grooves and slots
    84.
    发明授权
    File folder, box and panel designed with pre-perforated holes, grooves and slots 失效
    文件夹,盒子和面板设计有预穿孔,凹槽和槽

    公开(公告)号:US06439611B1

    公开(公告)日:2002-08-27

    申请号:US09694830

    申请日:2000-10-24

    申请人: Hung-Wei Chen

    发明人: Hung-Wei Chen

    IPC分类号: B42D1700

    摘要: A novel file folder, box and panel designed with pre-perforated holes, grooves and slots where the file folder at least comprises two pieces of panel, on which a plurality of holes, grooves, slots, and border indentations are pre-perforated. The file folder panel has at least a flap on its periphery. The pre-perforated holes, grooves and slots are fit for installing a variety of file clips. The pre-perforated holes and slots also permit fixing and winding the elastic trap. The flap, after being erected up in place, allows the file clip and elastic trap to band together. The invention provides a separate design of file folder panels and file clips to form varying combinations, functions and economical benefits as the end-user desires.

    摘要翻译: 一种新颖的文件夹,盒子和面板,其设计有预穿孔,凹槽和狭槽,其中文件夹至少包括两块面板,多个孔,凹槽,槽和边界凹陷在其上被预穿孔。 文件夹面板的外围至少有一个挡板。 预穿孔,槽和槽适合安装各种文件夹。 预穿孔孔和槽也可以固定和缠绕弹性陷阱。 襟翼在竖立之后就可以将文件夹和弹性陷阱捆绑在一起。 本发明提供文件夹面板和文件夹的单独设计,以形成最终用户期望的变化的组合,功能和经济效益。