公开(公告)号：US20070080387A1

公开(公告)日：2007-04-12

申请号：US11246318

申请日：2005-10-07

申请人： Sheng-Da Liu ,  Hung-Wei Chen ,  Chang-Yun Chang ,  Zhong Xuan ,  Ju-Wang Hsu

发明人： Sheng-Da Liu ,  Hung-Wei Chen ,  Chang-Yun Chang ,  Zhong Xuan ,  Ju-Wang Hsu

IPC分类号： H01L27/108

CPC分类号： H01L28/82 ,  H01L21/845 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： A one transistor (1T-RAM) bit cell and method for manufacture are provided. A metal-insulator-metal (MIM) capacitor structure and method of manufacturing it in an integrated process that includes a finFET transistor for the 1T-RAM bit cell is provided. In some embodiments, the finFET transistor and MIM capacitor are formed in a memory region and an asymmetric processing method is disclosed, which allows planar MOSFET transistors to be formed in another region of a single device. In some embodiments, the 1T-RAM cell and additional transistors may be combined to form a macro cell, multiple macro cells may form an integrated circuit. The MIM capacitors may include nanoparticles or nanostructures to increase the effective capacitance. The finFET transistors may be formed over an insulator. The MIM capacitors may be formed in interlevel insulator layers above the substrate. The process provided to manufacture the structure may advantageously use conventional photomasks.

摘要翻译： 提供一个晶体管（1T-RAM）位单元及其制造方法。 提供了一种金属 - 绝缘体金属（MIM）电容器结构及其制造方法，其集成工艺包括用于1T-RAM位元的finFET晶体管。 在一些实施例中，finFET晶体管和MIM电容器形成在存储区域中，并且公开了一种不对称处理方法，其允许在单个器件的另一个区域中形成平面MOSFET晶体管。 在一些实施例中，可以组合1T-RAM单元和附加晶体管以形成宏小区，多个宏小区可以形成集成电路。 MIM电容器可以包括纳米颗粒或纳米结构以增加有效电容。 finFET晶体管可以形成在绝缘体上。 MIM电容器可以形成在衬底上方的层间绝缘体层中。 提供用于制造结构的方法可以有利地使用常规的光掩模。

公开(公告)号：US07425740B2

公开(公告)日：2008-09-16

申请号：US11246318

申请日：2005-10-07

申请人： Sheng-Da Liu ,  Hung-Wei Chen ,  Chang-Yun Chang ,  Zhong Tang Xuan ,  Ju-Wang Hsu

发明人： Sheng-Da Liu ,  Hung-Wei Chen ,  Chang-Yun Chang ,  Zhong Tang Xuan ,  Ju-Wang Hsu

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L27/01 ,  H01L27/12

CPC分类号： H01L28/82 ,  H01L21/845 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： A one transistor (1T-RAM) bit cell and method for manufacture are provided. A metal-insulator-metal (MIM) capacitor structure and method of manufacturing it in an integrated process that includes a finFET transistor for the 1T-RAM bit cell is provided. In some embodiments, the finFET transistor and MIM capacitor are formed in a memory region and an asymmetric processing method is disclosed, which allows planar MOSFET transistors to be formed in another region of a single device. In some embodiments, the 1T-RAM cell and additional transistors may be combined to form a macro cell, multiple macro cells may form an integrated circuit. The MIM capacitors may include nanoparticles or nanostructures to increase the effective capacitance. The finFET transistors may be formed over an insulator. The MIM capacitors may be formed in interlevel insulator layers above the substrate. The process provided to manufacture the structure may advantageously use conventional photomasks.

摘要翻译： 提供一个晶体管（1T-RAM）位单元及其制造方法。 提供了一种金属 - 绝缘体金属（MIM）电容器结构及其制造方法，其集成工艺包括用于1T-RAM位元的finFET晶体管。 在一些实施例中，finFET晶体管和MIM电容器形成在存储区域中，并且公开了一种不对称处理方法，其允许在单个器件的另一个区域中形成平面MOSFET晶体管。 在一些实施例中，可以组合1T-RAM单元和附加晶体管以形成宏小区，多个宏小区可以形成集成电路。 MIM电容器可以包括纳米颗粒或纳米结构以增加有效电容。 finFET晶体管可以形成在绝缘体上。 MIM电容器可以形成在衬底上方的层间绝缘体层中。 提供用于制造结构的方法可以有利地使用常规的光掩模。

公开(公告)号：USRE45180E1

公开(公告)日：2014-10-07

申请号：US12792373

申请日：2010-06-02

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L21/311 ,  H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/085 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

摘要翻译： 提供了一种用于形成半导体器件的方法和使用该方法制造的器件。 在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。 通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。 沟槽部分地填充有电介质材料。 去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。

公开(公告)号：US07381649B2

公开(公告)日：2008-06-03

申请号：US11192494

申请日：2005-07-29

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

摘要翻译： 提供了一种用于形成半导体器件的方法和使用该方法制造的器件。 在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。 通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。 沟槽部分地填充有电介质材料。 去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。

公开(公告)号：US20060086987A1

公开(公告)日：2006-04-27

申请号：US10973966

申请日：2004-10-26

申请人： Hung-Wei Chen ,  Zhong Xuan ,  Shui-Ming Cheng ,  Sheng-Da Liu

发明人： Hung-Wei Chen ,  Zhong Xuan ,  Shui-Ming Cheng ,  Sheng-Da Liu

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78621 ,  H01L29/78684 ,  Y10S438/933

摘要： A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated extending a second depth within the substrate, the second depth not equal to the first depth.

摘要翻译： 半导体器件包括衬底，位于衬底上的第一器件，第一器件包括源和漏极，每个源极和漏极都位于衬底内延伸第一深度，第二器件位于衬底上，第二器件包括源极和 一个排水口，每个位于在衬底内延伸第二深度，第二深度不等于第一深度。

公开(公告)号：US07883979B2

公开(公告)日：2011-02-08

申请号：US10973966

申请日：2004-10-26

申请人： Hung-Wei Chen ,  Zhong Tang Xuan ,  Shui-Ming Cheng ,  Sheng-Da Liu

发明人： Hung-Wei Chen ,  Zhong Tang Xuan ,  Shui-Ming Cheng ,  Sheng-Da Liu

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78621 ,  H01L29/78684 ,  Y10S438/933

摘要： A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated extending a second depth within the substrate, the second depth not equal to the first depth.

摘要翻译： 半导体器件包括衬底，位于衬底上的第一器件，第一器件包括源和漏极，每个源极和漏极都位于衬底内延伸第一深度，第二器件位于衬底上，第二器件包括源极和 一个排水口，每个位于在衬底内延伸第二深度，第二深度不等于第一深度。

公开(公告)号：USRE45165E1

公开(公告)日：2014-09-30

申请号：US13372622

申请日：2012-02-14

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yu Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yu Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L29/06 ,  H01L27/085 ,  H01L29/04

CPC分类号： H01L29/1079 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

公开(公告)号：US20070026629A1

公开(公告)日：2007-02-01

申请号：US11192494

申请日：2005-07-29

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu

IPC分类号： H01L21/76 ,  H01L21/302

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

摘要翻译： 提供了一种用于形成半导体器件的方法和使用该方法制造的器件。 在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。 通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。 沟槽部分地填充有电介质材料。 去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。

公开(公告)号：US20050112817A1

公开(公告)日：2005-05-26

申请号：US10916023

申请日：2004-08-11

申请人： Shui-Ming Cheng ,  Hung-Wei Chen ,  Zhong Xuan

发明人： Shui-Ming Cheng ,  Hung-Wei Chen ,  Zhong Xuan

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/76 ,  H01L21/338

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The method further comprises forming a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, where the second semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device, and recessed source and drain regions disposed on either side of the gate structure.

摘要翻译： 一种方法包括在衬底中形成第一半导体器件，其中第一半导体器件包括栅极结构，设置在栅极结构的侧壁上的间隔物，间隔物具有第一厚度，以及升高的源极和漏极区域，其设置在 门结构。 所述方法还包括在所述衬底中形成第二半导体器件并与所述第一半导体器件电隔离，其中所述第二半导体器件包括栅极结构，设置在所述栅极结构的侧壁上的间隔物，所述间隔物的第二厚度小于 第一半导体器件的间隔物的第一厚度，以及设置在栅极结构的任一侧的凹陷的源极和漏极区域。

公开(公告)号：US20070128786A1

公开(公告)日：2007-06-07

申请号：US11673845

申请日：2007-02-12

申请人： Shui-Ming Cheng ,  Hung-Wei Chen ,  Zhong Xuan

发明人： Shui-Ming Cheng ,  Hung-Wei Chen ,  Zhong Xuan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The method further comprises forming a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, where the second semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device, and recessed source and drain regions disposed on either side of the gate structure.

摘要翻译： 一种方法包括在衬底中形成第一半导体器件，其中第一半导体器件包括栅极结构，设置在栅极结构的侧壁上的间隔物，间隔物具有第一厚度，以及升高的源极和漏极区域，其设置在 门结构。 所述方法还包括在所述衬底中形成第二半导体器件并与所述第一半导体器件电隔离，其中所述第二半导体器件包括栅极结构，设置在所述栅极结构的侧壁上的间隔物，所述间隔物的第二厚度小于 第一半导体器件的间隔物的第一厚度，以及设置在栅极结构的任一侧的凹陷的源极和漏极区域。