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    Semiconductor structure and method for integrating SOI devices and bulk devices
    2.
    发明授权
    Semiconductor structure and method for integrating SOI devices and bulk devices 有权
    用于集成SOI器件和散装器件的半导体结构和方法

    公开(公告)号：US07105897B2

    公开(公告)日：2006-09-12

    申请号：US10977236

    申请日：2004-10-28

    申请人： Hao-Yu Chen ,  Fu-Liang Yang ,  Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang

    发明人： Hao-Yu Chen ,  Fu-Liang Yang ,  Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

    摘要： This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.

    摘要翻译： 本发明公开了一种用于集成至少一个体器件和至少一个绝缘体上硅（SOI）器件的方法和半导体结构。 半导体结构包括具有SOI区域和体积区域的第一基板，在其上形成散装器件; 形成在SOI区域的第一基板上的绝缘层; 以及在其上形成有SOI器件的第二衬底，堆叠在绝缘层上。 第一基板的表面不在与第二基板的表面基本相同的平面上。

    CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof
    3.
    发明授权
    CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof 有权
    在混合晶体取向上制造的CMOS逻辑门及其形成方法

    公开(公告)号：US07208815B2

    公开(公告)日：2007-04-24

    申请号：US10989080

    申请日：2004-11-15

    申请人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L29/04

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/7842 ,  H01L29/785

    摘要： In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

    摘要翻译： 在本发明的优选实施例中，描述了使用SOI和混合衬底取向形成CMOS器件的方法。 根据优选实施例，衬底可以具有多个晶体取向。 衬底中的一个逻辑门可以包括在一个晶体取向上的至少一个N-FET和另一个晶体取向上的至少一个P-FET。 衬底中的另一个逻辑门可以包括至少一个N-FET和至少一个相同取向的P-FET。 替代实施例还包括确定基板的优选解理平面并且考虑到它们各自优选的解理平面使基板相对于彼此定向。 在优选实施例中，解理平面不平行。

    CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof
    7.
    发明申请
    CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof 有权
    在混合晶体取向上制造的CMOS逻辑门及其形成方法

    公开(公告)号：US20060049460A1

    公开(公告)日：2006-03-09

    申请号：US10989080

    申请日：2004-11-15

    申请人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L27/12

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/7842 ,  H01L29/785

    摘要： In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

    摘要翻译： 在本发明的优选实施例中，描述了使用SOI和混合衬底取向形成CMOS器件的方法。 根据优选实施例，衬底可以具有多个晶体取向。 衬底中的一个逻辑门可以包括在一个晶体取向上的至少一个N-FET和另一个晶体取向上的至少一个P-FET。 衬底中的另一个逻辑门可以包括至少一个N-FET和至少一个相同取向的P-FET。 替代实施例还包括确定基板的优选解理平面并且考虑到它们各自优选的解理平面使基板相对于彼此定向。 在优选实施例中，解理平面不平行。

    Encapsulated damascene with improved overlayer adhesion
    8.
    发明授权
    Encapsulated damascene with improved overlayer adhesion 有权
    具有改进的覆盖层附着力的封装的镶嵌

    公开(公告)号：US07737556B2

    公开(公告)日：2010-06-15

    申请号：US11241355

    申请日：2005-09-30

    申请人： Chao-Hsiung Wang ,  Ping-Kun Wu

    发明人： Chao-Hsiung Wang ,  Ping-Kun Wu

    IPC分类号： H01L23/48

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device comprising a partially embedded and encapsulated damascene structure and method for forming the same to improve adhesion to an overlying dielectric layer, the integrated circuit device including a conductive material partially embedded in an opening formed in a dielectric layer; wherein said conductive material is encapsulated with a first barrier layer comprising sidewall and bottom portions and a second barrier layer covering a top portion, said conductive material and first barrier layer sidewall portions extending to a predetermined height above an upper surface of the dielectric layer to form a partially embedded damascene.

    摘要翻译： 一种集成电路装置，包括部分嵌入和封装的镶嵌结构及其形成方法以改善与上覆介质层的粘合性，所述集成电路器件包括部分地嵌入形成在介电层中的开口中的导电材料; 其中所述导电材料被封装有包括侧壁和底部的第一阻挡层和覆盖顶部的第二阻挡层，所述导电材料和第一阻挡层侧壁部分延伸到介电层的上表面上方的预定高度以形成 部分嵌入的镶嵌。

    Method for forming a multi-layer seed layer for improved Cu ECP
    9.
    发明授权
    Method for forming a multi-layer seed layer for improved Cu ECP 有权
    用于形成用于改善Cu ECP的多层种子层的方法

    公开(公告)号：US07265038B2

    公开(公告)日：2007-09-04

    申请号：US10723509

    申请日：2003-11-25

    申请人： Ping-Kun Wu ,  Horng-Huei Tseng ,  Chine-Gie Lo ,  Chao-Hsiung Wang ,  Shau-Lin Shue

    发明人： Ping-Kun Wu ,  Horng-Huei Tseng ,  Chine-Gie Lo ,  Chao-Hsiung Wang ,  Shau-Lin Shue

    IPC分类号： H01L21/26

    CPC分类号： H01L21/76807 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.

    摘要翻译： 铜填充镶嵌结构及其形成方法，包括提供包括半导体衬底的衬底; 在所述基板上形成绝缘体层; 通过所述绝缘体层的厚度部分形成镶嵌开口; 形成扩散阻挡层以使所述镶嵌开口成线; 形成覆盖所述扩散阻挡层的第一晶种层; 用包含选自氩，氮，氢和NH 3的等离子体源气体的第一处理等离子体原位处理第一籽晶层; 形成覆盖所述第一种子层的第二种子层; 根据电化学电镀（ECP）工艺形成覆盖在第二晶种层上的铜层以填充镶嵌开口; 并且平坦化铜层以形成金属互连结构。

    Encapsulated damascene with improved overlayer adhesion
    10.
    发明申请
    Encapsulated damascene with improved overlayer adhesion 有权
    具有改进的覆盖层附着力的封装的镶嵌

    公开(公告)号：US20070075428A1

    公开(公告)日：2007-04-05

    申请号：US11241355

    申请日：2005-09-30

    申请人： Chao-Hsiung Wang ,  Ping-Kun Wu

    发明人： Chao-Hsiung Wang ,  Ping-Kun Wu

    IPC分类号： H01L23/52 ,  H01L21/44

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device comprising a partially embedded and encapsulated damascene structure and method for forming the same to improve adhesion to an overlying dielectric layer, the integrated circuit device including a conductive material partially embedded in an opening formed in a dielectric layer; wherein said conductive material is encapsulated with a first barrier layer comprising sidewall and bottom portions and a second barrier layer covering a top portion, said conductive material and first barrier layer sidewall portions extending to a predetermined height above an upper surface of the dielectric layer to form a partially embedded damascene.

    摘要翻译： 一种集成电路装置，包括部分嵌入和封装的镶嵌结构及其形成方法以改善与上覆介质层的粘合性，所述集成电路器件包括部分地嵌入形成在介电层中的开口中的导电材料; 其中所述导电材料被封装有包括侧壁和底部的第一阻挡层和覆盖顶部的第二阻挡层，所述导电材料和第一阻挡层侧壁部分延伸到介电层的上表面上方的预定高度以形成 部分嵌入的镶嵌。