公开(公告)号：US06818519B2

公开(公告)日：2004-11-16

申请号：US10252753

申请日：2002-09-23

申请人： Sunfei Fang ,  Lawrence Clevenger

发明人： Sunfei Fang ,  Lawrence Clevenger

IPC分类号： H01L21336

CPC分类号： H01L29/66553 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76816 ,  H01L29/6656 ,  H01L29/6659

摘要： A method of forming organic spacers using an N2 plasma or N2 containing plasma anisotropic etchant, and using such organic spacers for forming features on a semiconductor structure such as vias having a smaller dimension than can be defined by lithographic techniques Other features formed according to the teachings of this invention include Source/Drain (S/D) areas, LDD/extension areas and graded junctions with larger S/D silicide/contact areas. The process for forming the organic spacers comprises conformally coating a patterned semiconductor structure with an organic material such as, for example, an antireflective coating. The coated structure is then anisotropically etched with N2 plasma or N2 containing plasma which forms the organic spacers. Organic spacers may be formed by the method of this invention or any other known method and used to form other device features such as (i) larger S/D contact areas, which may include graded junctions; and (ii) larger S/D contact areas and LDD/extensions, which may also include graded junctions with a single implant step.

公开(公告)号：US06624526B2

公开(公告)日：2003-09-23

申请号：US09872325

申请日：2001-06-01

申请人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

发明人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

IPC分类号： H01L2711

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

摘要翻译： 描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供 衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。 本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。

公开(公告)号：US06268293B1

公开(公告)日：2001-07-31

申请号：US09442956

申请日：1999-11-18

申请人： Lawrence Clevenger ,  Greg Costrini ,  Dave Dobuzinsky ,  Yoichi Otani ,  Thomas Rupp ,  Viraj Sardesai

发明人： Lawrence Clevenger ,  Greg Costrini ,  Dave Dobuzinsky ,  Yoichi Otani ,  Thomas Rupp ,  Viraj Sardesai

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C4F8, 20-80 sccm of CO, 2-30 sccm of O2 and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

摘要翻译： 在集成电路芯片中形成导线的镶嵌方法。 通过在50-400mTorr的压力下以500至3000瓦的电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2-30sccm的C 4 F 8，20-80sccm的CO，2-30sccm的O 2和50-400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。