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    ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE
    84.
    发明申请
    ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE 有权

    公开(公告)号：US20230068702A1

    公开(公告)日：2023-03-02

    申请号：US17591406

    申请日：2022-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Jung Sheng Hoei ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick R. Khayat

    IPC: G06F3/06

    Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

    MEMORY DEVICES INCLUDING INDIUM-CONTAINING MATERIALS, AND RELATED ELECTRONIC SYSTEMS
    87.
    发明申请
    MEMORY DEVICES INCLUDING INDIUM-CONTAINING MATERIALS, AND RELATED ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20220406941A1

    公开(公告)日：2022-12-22

    申请号：US17821414

    申请日：2022-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Guangyu Huang ,  Haitao Liu ,  Akira Goda

    IPC: H01L29/786 ,  H01L27/11529 ,  H01L27/11573 ,  H01L29/66

    Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.

    MULTI-DECKS MEMORY DEVICE INCLUDING INTER-DECK SWITCHES
    89.
    发明申请
    MULTI-DECKS MEMORY DEVICE INCLUDING INTER-DECK SWITCHES 有权

    公开(公告)号：US20220284959A1

    公开(公告)日：2022-09-08

    申请号：US17706087

    申请日：2022-03-28

    Applicant: Micron Technology, Inc.

    Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

    IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

    Sequential voltage ramp-down of access lines of non-volatile memory device
    90.
    发明授权
    Sequential voltage ramp-down of access lines of non-volatile memory device 有权

    公开(公告)号：US11417396B2

    公开(公告)日：2022-08-16

    申请号：US17067550

    申请日：2020-10-09

    Applicant: Micron Technology, Inc.

    Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

    IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

    Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

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