公开(公告)号：US11182085B2

公开(公告)日：2021-11-23

申请号：US16555293

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/06

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

公开(公告)号：US11158364B2

公开(公告)日：2021-10-26

申请号：US16428625

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US20210319826A1

公开(公告)日：2021-10-14

申请号：US16844182

申请日：2020-04-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William Chad Waldrop ,  Daniel B. Penney

IPC: G11C11/4076 ,  H04L25/03 ,  G11C11/4096 ,  G11C11/4093

Abstract: Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

公开(公告)号：US11139015B2

公开(公告)日：2021-10-05

申请号：US16459520

申请日：2019-07-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be tracked by each memory device. When a memory device determines that an accessed word line is an aggressor word line, the memory device alerts other memory devices of the apparatus. The memory devices may then perform targeted refresh operations on victim word lines of the aggressor word line.

公开(公告)号：US11139008B2

公开(公告)日：2021-10-05

申请号：US16779866

申请日：2020-02-03

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.

公开(公告)号：US20210304809A1

公开(公告)日：2021-09-30

申请号：US16834409

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： William C. Waldrop ,  Daniel B. Penney

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10

Abstract: Systems and methods are provided that provide protection from undesired latching that may be caused by indeterminate interamble periods in an input/output (DQS) signal. Interamble compensation circuitry may filter out interamble states of the DQS signal from provision to downstream components that use the DQS signal to identify data latching times.

公开(公告)号：US20210241813A1

公开(公告)日：2021-08-05

申请号：US16781763

申请日：2020-02-04

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Wiliiam C. Waldrop

IPC: G11C11/4076 ,  H03K3/037 ,  H03K19/20

Abstract: Memory devices receive a data signal and an accompanying data strobing signal, which informs the device that data is ready for latching. The data strobing signal enables capturing the data while the data signal transitions from a logic high to a logic low or vice versa, resulting in an indeterminate output (e.g., between 0 and 1). The indeterminate value may cause metastability in memory operations using the indeterminate output. To prevent or reduce metastability, a cascaded timing arbiter latch includes cascaded alternating NAND timing arbiters and NOR timing arbiters. In some embodiments, these logic gates are connected to transistors above and below the cascaded timing arbiters. The cascaded timing arbiters and/or transistors provide amplification on a feedback path of the latch. In other embodiments, the cascaded timing arbiters are isolated by inverters and are not connected to transistors. This embodiment reduces capacitive loading on nodes of the internal feedback path.

公开(公告)号：US10991416B1

公开(公告)日：2021-04-27

申请号：US16803486

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Brian J. Ladner ,  Daniel B. Penney

IPC: G06F13/28 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093 ,  H03K19/20

Abstract: Systems and methods may involve circuitry that receives a first transition of a clocking signal. The circuitry may also to enable a compensation circuit characterized by a capacitance in response to the first transition of the clocking signal and may receive subsequent transitions of the clocking signal. The circuitry may also apply the capacitance to the subsequent transitions of the clocking signal after enabling the compensation circuit to generate a compensated clocking signal characterized by an adjusted duty cycle relative to a duty cycle of the clocking signal.

公开(公告)号：US20210118483A1

公开(公告)日：2021-04-22

申请号：US17136760

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/22

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

公开(公告)号：US10985738B1

公开(公告)日：2021-04-20

申请号：US16781875

申请日：2020-02-04

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: H03K19/0175 ,  H03K3/356 ,  G11C11/4093

Abstract: Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement of transistors is opposite the second series arrangement of transistors. The output of the first series arrangement of transistors is coupled to a first node and selectively couples the first node to a first voltage based on an input signal. The output of the second series arrangement of transistors is coupled to a second node and couples the second node to the first voltage based on an input signal. The first node and the second node are coupled to the first voltage at different times. The series arrangements of transistors enables faster level shifting over conventional level shifters.