公开(公告)号：US11887688B2

公开(公告)日：2024-01-30

申请号：US17511314

申请日：2021-10-26

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Efrem Bolandrina

IPC: G11C7/10 ,  G11C8/18

CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1048 ,  G11C8/18

Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

公开(公告)号：US11887663B2

公开(公告)日：2024-01-30

申请号：US18079494

申请日：2022-12-12

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0045

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array based on the read request. The control circuit is additionally configured to count a number of the plurality of memory cells that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit is further configured to apply a second voltage at the second duration to the memory array. The control circuit is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

公开(公告)号：US20220357791A1

公开(公告)日：2022-11-10

申请号：US17870696

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F1/3234 ,  G06F13/16 ,  G11C5/14

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

公开(公告)号：US20220172750A1

公开(公告)日：2022-06-02

申请号：US17671000

申请日：2022-02-14

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C5/14 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

公开(公告)号：US20220091933A1

公开(公告)日：2022-03-24

申请号：US17479798

申请日：2021-09-20

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Graziano Mirichigni ,  Ferdinando Bedeschi

IPC: G06F11/10 ,  G06F12/16

Abstract: A memory apparatus and a method for operating the same. The method includes performing a read operation on a set of memory cells, detecting an error in data read from the set of memory cells based on an error correction code (ECC) operation performed on the data, and performing a scrubbing operation or a refreshing operation on the set of memory cells according to a detecting result.

公开(公告)号：US11074949B2

公开(公告)日：2021-07-27

申请号：US16515629

申请日：2019-07-18

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Efrem Bolandrina

IPC: G11C11/408 ,  G11C8/08 ,  G06F3/06 ,  G11C11/22 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4096

Abstract: Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.

公开(公告)号：US10915321B2

公开(公告)日：2021-02-09

申请号：US16105846

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

IPC: G06F9/30 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C13/00

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

公开(公告)号：US10796731B2

公开(公告)日：2020-10-06

申请号：US16513115

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C7/00 ,  G11C5/14 ,  G06F13/16 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

公开(公告)号：US10779147B2

公开(公告)日：2020-09-15

申请号：US14547011

申请日：2014-11-18

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Danilo Caraccio

IPC: G06F12/10 ,  H04W4/80 ,  H04W4/00 ,  G06F12/1027

Abstract: Systems and methods for vendor-agnostic access to non-volatile memory of a wireless memory tag include: detecting, via a wireless memory host, a wireless memory tag; providing a vendor-agnostic command to the wireless memory tag to affect a change in a register-based interface of the wireless memory tag, wherein the change results in reading data from non-volatile memory of the wireless memory tag, writing data to the non-volatile memory of the wireless memory tag, or both.

公开(公告)号：US10740263B2

公开(公告)日：2020-08-11

申请号：US16058793

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C8/06

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.