公开(公告)号：US20200075076A1

公开(公告)日：2020-03-05

申请号：US16121224

申请日：2018-09-04

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Suryanarayana B. Tatapudi ,  Huy T. Vo ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G11C11/4091 ,  G11C11/4094

Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.

公开(公告)号：US10534394B2

公开(公告)日：2020-01-14

申请号：US16138517

申请日：2018-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G06F1/06 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093 ,  G11C7/00 ,  G11C7/10 ,  G11C19/00 ,  G11C7/22 ,  G11C11/408 ,  G06F1/12

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent mad commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：US20190385654A1

公开(公告)日：2019-12-19

申请号：US16551981

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C8/18 ,  G11C16/08 ,  G11C16/28 ,  G11C16/32

Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.

公开(公告)号：US20190317545A1

公开(公告)日：2019-10-17

申请号：US16448297

申请日：2019-06-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G06F1/06 ,  G06F1/12 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/10 ,  G11C19/00 ,  G11C11/408 ,  G11C11/4093 ,  G11C7/22 ,  G11C7/00

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：US20190311753A1

公开(公告)日：2019-10-10

申请号：US16452436

申请日：2019-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/10

Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

公开(公告)号：US10437514B2

公开(公告)日：2019-10-08

申请号：US15722769

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  John D. Porter

IPC: G06F3/06 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4074

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.

公开(公告)号：US20190265913A1

公开(公告)日：2019-08-29

申请号：US16413475

申请日：2019-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  John D. Porter

IPC: G06F3/06

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing, an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.

公开(公告)号：US10395704B2

公开(公告)日：2019-08-27

申请号：US15853514

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C8/18 ,  G11C16/32 ,  G11C16/28 ,  G11C16/08

Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.

公开(公告)号：US20190139620A1

公开(公告)日：2019-05-09

申请号：US16019254

申请日：2018-06-26

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee

IPC: G11C29/50 ,  G11C29/02

Abstract: Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

公开(公告)号：US20190066741A1

公开(公告)日：2019-02-28

申请号：US15692993

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee

IPC: G11C7/22

Abstract: Apparatuses and methods for providing active an inactive clock signals are disclosed. An example apparatus includes an input clock buffer and a clock divider circuit. The input clock buffer includes a receiver circuit configured to receive first and second clock signals or first and second constant voltages. The receiver circuit is further configured to provide first and second output signals based on the complementary clock signals or the first and second constant voltages. The first and second clock signals are complementary and the second constant voltage is less than the first constant voltage. The clock divider circuit is configured to receive the first and second output signals and provide multiphase clock signals based on the first and second output signals from the input clock buffer.