公开(公告)号：US11646751B2

公开(公告)日：2023-05-09

申请号：US17348654

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Markus H. Geiger ,  Matthew A. Prather ,  Sujeet Ayyapureddi ,  C. Omar Benitez ,  Dennis Montierth

IPC: H03M13/09 ,  G06F11/10

CPC classification number: H03M13/095 ,  G06F11/1076

Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

公开(公告)号：US11474820B2

公开(公告)日：2022-10-18

申请号：US17156065

申请日：2021-01-22

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F9/30 ,  G06F3/06 ,  G06F30/331

Abstract: Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

公开(公告)号：US20220284979A1

公开(公告)日：2022-09-08

申请号：US17750103

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Randall J. Rooney

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/406 ,  G11C29/00

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom.

公开(公告)号：US20220171534A1

公开(公告)日：2022-06-02

申请号：US17544629

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Matthew A. Prather

IPC: G06F3/06

Abstract: Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.

公开(公告)号：US20220147267A1

公开(公告)日：2022-05-12

申请号：US17517107

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather ,  Neal J. Koyle

IPC: G06F3/06

Abstract: Methods for operating a memory system are disclosed herein. In one embodiment, a method comprises receiving first data to be written at a logical address of a memory array, storing the first data at a first physical address corresponding to the logical address, and remapping the logical address to a second physical address, for example, using a soft post package repair operation. The method can further include receiving second data different from the first data to be written at the logical address, storing the second data at the second physical address, and remapping the logical address to the first physical address. In some embodiments, the method can comprise storing first and second ECC data corresponding to the first and second data, respectively. The method can further comprise outputting the first data and/or the second ECC data in response to a read request corresponding to the logical address.

公开(公告)号：US20220130484A1

公开(公告)日：2022-04-28

申请号：US17081731

申请日：2020-10-27

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Randall J. Rooney

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4074

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom.

公开(公告)号：US20220084565A1

公开(公告)日：2022-03-17

申请号：US17534230

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Randall J. Rooney

IPC: G11C7/10 ,  G06F11/30 ,  G11C11/4093

Abstract: Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

公开(公告)号：US20210350842A1

公开(公告)日：2021-11-11

申请号：US17379422

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Thomas H. Kinsley

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/407

Abstract: Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.

公开(公告)号：US20210334159A1

公开(公告)日：2021-10-28

申请号：US17372453

申请日：2021-07-10

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Randall J. Rooney

IPC: G06F11/10 ,  G11C13/00 ,  G06F11/07

Abstract: An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

公开(公告)号：US10983934B2

公开(公告)日：2021-04-20

申请号：US16931144

申请日：2020-07-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G11C5/14 ,  G06F13/16 ,  G06F5/06 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3206

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.