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公开(公告)号：US20130184865A1
公开(公告)日：2013-07-18
申请号：US13616245
申请日：2012-09-14
IPC分类号： G05B19/418
CPC分类号： G05D1/0291 , G05B19/41815 , G05B2219/39146 , G05B2219/39168 , G05D1/0274 , G05D2201/0207 , G08G1/20
摘要： Techniques are provided for discovery and monitoring of an environment using a plurality of robots. A plurality of robots navigate an environment by determining a navigation buffer for each of the robots; and allowing each of the robots to navigate within the environment while maintaining a substantially minimum distance from other robots, wherein the substantially minimum distance corresponds to the navigation buffer, and wherein a size of each of the navigation buffers is reduced over time based on a percentage of the environment that remains to be navigated. The robots can also navigate an environment by obtaining a discretization of the environment to a plurality of discrete regions; and determining a next unvisited discrete region for one of the plurality of robots to explore in the exemplary environment using a breadth-first search. The plurality of discrete regions can be, for example, a plurality of real or virtual tiles.
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公开(公告)号：US20130184864A1
公开(公告)日：2013-07-18
申请号：US13348846
申请日：2012-01-12
IPC分类号： G05B19/418
CPC分类号： G05D1/0291 , G05B19/41815 , G05B2219/39146 , G05B2219/39168 , G05D1/0274 , G05D2201/0207 , G08G1/20
摘要： Techniques are provided for discovery and monitoring of an environment using a plurality of robots. A plurality of robots navigate an environment by determining a navigation buffer for each of the robots; and allowing each of the robots to navigate within the environment while maintaining a substantially minimum distance from other robots, wherein the substantially minimum distance corresponds to the navigation buffer, and wherein a size of each of the navigation buffers is reduced over time based on a percentage of the environment that remains to be navigated. The robots can also navigate an environment by obtaining a discretization of the environment to a plurality of discrete regions; and determining a next unvisited discrete region for one of the plurality of robots to explore in the exemplary environment using a breadth-first search. The plurality of discrete regions can be, for example, a plurality of real or virtual tiles.
摘要翻译： 提供了使用多个机器人发现和监测环境的技术。 多个机器人通过为每个机器人确定导航缓冲器来导航环境; 并且允许每个机器人在环境中导航，同时保持与其他机器人基本上最小的距离，其中基本上最小距离对应于导航缓冲器，并且其中每个导航缓冲器的尺寸随时间而减少，基于百分比 的环境仍有待导航。 机器人还可以通过获得对多个离散区域的环境离散度来导航环境; 以及确定所述多个机器人中的一个机器人的下一个未访问离散区域，以在所述示例性环境中使用宽度优先搜索进行探索。 多个离散区域可以是例如多个实际瓦片或虚拟瓦片。
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83.发明申请Effective Memory Clustering to Minimize Page Fault and Optimize Memory Utilization 失效有效的内存集群，最大限度地减少页面错误并优化内存利用率公开(公告)号：US20120060013A1
公开(公告)日：2012-03-08
申请号：US13292256
申请日：2011-11-09
申请人： Maharaj Mukherjee
发明人： Maharaj Mukherjee
IPC分类号： G06F12/08
CPC分类号： G06F11/3471 , G06F11/3409 , G06F2201/885
摘要： An embodiment of the invention provides a method for organizing data addresses within a virtual address space to reduce the number of data fetches to a cloud computing environment. More specifically, data access requests to the cloud computing environment are monitored to identifying data addresses having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein the creating of the memory page includes creating a cross-sectional partition from the multi-dimensional cluster. The multi-dimensional clusters and the memory page are stored in the cloud computing environment. A request for a data object in the cloud computing environment is received from a user interface. The data address corresponding to the data object is identified and mapped to the multi-dimensional cluster and/or the memory page. The memory page is transferred to the user interface.
摘要翻译： 本发明的实施例提供了一种用于组织虚拟地址空间内的数据地址以减少到云计算环境的数据获取数量的方法。 更具体地，监视对云计算环境的数据访问请求以识别具有相似属性的数据地址。 基于监视来创建多维集群，以对具有相似属性的数据地址进行分组。 从多维集群创建存储器页面，其中创建存储器页面包括从多维集群创建横截面分区。 多维集群和内存页面存储在云计算环境中。 从用户界面接收对云计算环境中的数据对象的请求。 识别对应于数据对象的数据地址并映射到多维集群和/或存储器页面。 内存页面被传送到用户界面。
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84.发明授权Method and system for obtaining bounds on process parameters for OPC-verification 有权用于获取OPC验证过程参数界限的方法和系统公开(公告)号：US08059884B2
公开(公告)日：2011-11-15
申请号：US11937073
申请日：2007-11-08
IPC分类号： G06K9/20
CPC分类号： G06K9/036 , G03F7/70441
摘要： Embodiments of the present invention provide a method of performing printability verification of a mask layout. The method includes creating one or more tight clusters; computing a set of process parameters associated with a point on said mask; comparing said set of process parameters to said one or more tight clusters; and reporting an error when at least one of said process parameters is away from said one or more tight clusters.
摘要翻译： 本发明的实施例提供了一种执行掩模布局的可印刷性验证的方法。 该方法包括创建一个或多个紧密簇; 计算与所述掩模上的点相关联的一组过程参数; 将所述一组过程参数与所述一个或多个紧密簇进行比较; 并且当至少一个所述过程参数远离所述一个或多个紧密簇时报告错误。
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85.发明授权Methodology and system for determining numerical errors in pixel-based imaging simulation in designing lithographic masks 有权在设计光刻掩模时，基于像素的成像仿真中确定数值误差的方法和系统公开(公告)号：US07975244B2
公开(公告)日：2011-07-05
申请号：US12019125
申请日：2008-01-24
IPC分类号： G06F17/50
摘要： A method is provided for designing a mask that includes the use of a pixel-based simulation of a lithographic process model, in which test structures are designed for determining numerical and discretization errors associated with the pixel grid as opposed to other model inaccuracies. The test structure has a plurality of rows of the same sequence of features, but each row is offset from other rows along an x-direction by a multiple of a minimum step size, such as used in modifying masks during optical proximity correction. The images for each row are simulated with a lithographic model that uses the selected pixel-grid size and the differences between row images are compared. If the differences between rows exceed or violate a predetermined criterion, the pixel grid size may be modified to minimize discretization and/or numerical errors due to the choice of pixel grid size.
摘要翻译： 提供了一种用于设计包括使用光刻处理模型的基于像素的仿真的掩模的方法，其中测试结构被设计用于确定与像素网格相关的数值和离散化误差，而不是其他模型不准确。 测试结构具有相同序列特征的多行，但是每一行都沿着x方向与其他行偏移最小步长的倍数，例如在光学邻近校正期间用于修改掩模。 使用所选择的像素网格大小的光刻模型来模拟每行的图像，并比较行图像之间的差异。 如果行之间的差异超过或违反预定标准，则可以修改像素网格大小以使由于像素网格大小的选择而导致的离散化和/或数值误差最小化。
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86.发明授权Methodology to improve turnaround for integrated circuit design using geometrical hierarchy 失效使用几何层次结构改善集成电路设计周转的方法公开(公告)号：US07669175B2
公开(公告)日：2010-02-23
申请号：US11747485
申请日：2007-05-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.
摘要翻译： 提供了一种设计用于制造集成电路的布局的方法，其中，通过设计处理的计算密集部分（诸如通过掩模设计传送的图像的模拟）或电路的电特性的模拟被更高效地执行 仅在具有相同几何上下文的计算子单元的单个实例上执行这样的计算。 因此，不是基于功能布局执行这样的计算，而是通过典型的设计过程步骤导致功能层次结构的显着平坦化，从而增加计算成本，本发明对基于几何的层次结构存储的计算子单元进行模拟 上下文，最大限度地降低了模拟成本。 随后根据功能布局组合得到的模拟结果。
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公开(公告)号：US20090273441A1
公开(公告)日：2009-11-05
申请号：US12115041
申请日：2008-05-05
申请人： Maharaj Mukherjee
发明人： Maharaj Mukherjee
IPC分类号： G05B19/045
CPC分类号： A47C31/126
摘要： A method for adjusting the components within an office space includes adjusting to a preferred setting at least one of a plurality of physical features of at least one of a plurality of components for at least one of a plurality of persons; and storing the preferred setting for the at least one person. One of the persons is identified from information about that person (e.g. biometric information), and for the identified person at least one of the physical features of at least one of the components is adjusted to the preferred setting.
摘要翻译： 一种用于调整办公空间内的部件的方法包括：针对至少一个人的多个部件中的至少一个部件的多个物理特征中的至少一个物理特征来调整优选设置; 以及存储所述至少一个人的优选设置。 根据关于该人的信息（例如，生物特征信息）识别其中一个人，并且对于所识别的人，将至少一个组件的至少一个物理特征调整到优选设置。
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公开(公告)号：US07503028B2
公开(公告)日：2009-03-10
申请号：US11306750
申请日：2006-01-10
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。
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89.发明申请公开(公告)号：US20080163153A1
公开(公告)日：2008-07-03
申请号：US11619320
申请日：2007-01-03
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the designed mask layout is simulated using a simplified version of the mask layout with a lower accuracy to generate a lower accuracy simulated image. Where the lower accuracy simulated image is determined as potentially including an error, a further simulation of the designated portion of the mask layout with a higher accuracy will be performed.
摘要翻译： 公开了一种用于验证光刻工艺的掩模布局的可印刷性的方法，系统和计算机程序产品。 使用精度较低的掩模布局的简化版本来模拟设计的掩模布局的光刻工艺的模拟，以产生较低精度的模拟图像。 在将低精度模拟图像确定为潜在地包括错误的情况下，将执行具有更高精度的掩模布局的指定部分的进一步模拟。
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公开(公告)号：US20080127027A1
公开(公告)日：2008-05-29
申请号：US11555854
申请日：2006-11-02
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A fast method of verifying a lithographic mask design is provided wherein catastrophic errors are identified by iteratively simulating and verifying images for the mask layout using progressively more accurate image models, including optical and resist models. Progressively accurate optical models include SOCS kernels that provide successively less influence. Corresponding resist models are constructed that may include only SOCS kernel terms corresponding to the optical model, or may include image trait terms of varying influence ranges. Errors associated with excessive light, such as bridging, side-lobe or SRAF printing errors, are preferably identified with bright field simulations, while errors associated with insufficient light, such as necking or line-end shortening overlay errors, are preferably identified with dark field simulations.
摘要翻译： 提供了一种验证光刻掩模设计的快速方法，其中通过使用逐渐更精确的图像模型（包括光学和抗蚀剂模型）迭代地模拟和验证用于掩模布局的图像来识别灾难性错误。 逐步准确的光学模型包括提供连续影响较小的SOCS内核。 构造相应的抗蚀剂模型，其可以仅包括对应于光学模型的SOCS核项，或者可以包括不同影响范围的图像特征项。 优选用亮场模拟来识别与过多光线相关的错误，例如桥接，旁瓣或SRAF打印错误，而与光线不足相关的错误，例如颈缩或线端缩短覆盖误差，优选地用暗场 模拟。
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