摘要:
An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要:
An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要:
A semiconductor process in which a first nitrogen bearing oxide is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then formed on the nitrogen bearing oxide. The first oxide and the silicon nitride layer are then patterned to expose an upper surface of the substrate over a trench region of the substrate. An isolation trench is then etched into the trench region of the substrate and a nitrogen bearing liner oxide is then formed on sidewalls and a floor of the trench. An isolation dielectric is then formed within the trench and, thereafter, the silicon nitride layer is removed from the wafer. A suitable thickness of the first nitrogen bearing oxide and of the liner oxide is in the range of approximately 30 to 100 angstroms. A consumption of adjacent active regions caused by the thermal oxidation process is preferably less than approximately 50 angstroms.
摘要:
A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.
摘要:
The present invention advantageously provides a method for determining lithographic misalignment of a via relative to an electrically active area. An electrically measured test structure is provided which is designed to have targeted via areas shifted from the midline(s) of a targeted active area(s). Further, the test structure is designed to have a test pad(s) that electrically communicates with the targeted active area(s). Design specifications of the test structure require the targeted via areas to be offset from the midline(s) of the active area(s) by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to conductors coupled to each of the vias while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a via is misaligned from its desired location. Using the electrical responses for all the vias, it is possible to determine the direction and amount of misalignment.
摘要:
Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnected by imaging using a stitching reticle having an exposure field overlapping a plurality of the regions. The combination of reticle-imaged fields effectively increases the size of a field formed using a step and repeat technique while achieving high imaging resolution within the combined regions. Similarly, a plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are interconnected using a stitch mask and etch operation that combines the regions.
摘要:
A process is provided for forming a trench isolation structure which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. As a result, the lateral width of the isolation structure may be decreased without significantly increasing the capacitance between those active areas. In an embodiment, a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner is thermally grown upon the sidewalls and base of the trench. A low K dielectric material is formed within the trench such that its upper surface is level with the upper surface of the substrate. A fill oxide is then formed across the upper surface of the dielectric material. The resulting trench isolation structure includes a low K dielectric material encapsulated by some form of oxide. The trench isolation structure is less likely to experience current leakage during the operation of an ensuing integrated circuit employing the isolation structure.
摘要:
A semiconductor fabrication process in which nitrogen is incorporated into the transistor gate without significantly increasing the resistivity of the source/drain region. The incorporation of nitrogen into the gate structure substantially reduces the migration of impurity dopants from the silicon gate into the transistor channel region resulting in a more stable and reliable transistor. In one embodiment, a tail of the nitrogen impurity distribution incorporated into the gate structure extends into the channel region of the semiconductor substrate. In this embodiment, the nitrogen within the channel region prevents excessive lateral diffusion of source/drain impurities thereby permitting the fabrication of deep sub-micron transistors.
摘要:
An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide. In this manner, a highly miniaturized IGFET can be provided with densely-packed gate, source and drain contacts without the need for sidewall spacers adjacent to the gate.
摘要:
A method of forming an IGFET includes forming a trench in a substrate, forming spacers on opposing sidewalls of the trench, forming a gate insulator on a bottom surface of the trench between the spacers, forming a gate electrode on the gate insulator and the spacers, removing at least portions of the spacers to form voids in the trench after forming the gate electrode, implanting localized source and drain regions through the voids and through the bottom surface of the trench outside the gate electrode, and forming a source and drain in the substrate that include the localized source and drain regions adjacent to the bottom surface of the trench. The localized source and drain regions provide accurately positioned channel junctions beneath the trench. Furthermore, the dopant concentration of the localized source and drain regions is controlled by the amount of the spacers, if any, left intact when the localized source and drain regions are implanted after removing the portions of the spacers.