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公开(公告)号：US20200341847A1
公开(公告)日：2020-10-29
申请号：US16839438
申请日：2020-04-03
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
Abstract: Methods, systems, and devices for performing safety event detection for a memory device are described. For example, a memory array of a memory device may operate in a first mode of operation (e.g., a normal mode of operation). An event associated with a reduction of data integrity for the memory array may be detected. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. Based on the detected event, it may be determined whether to adjust the operation of the memory device to a second mode of operation (e.g., a safe mode of operation). The second mode of operation may correspond to a mode of operation that increases data retention characteristics.
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公开(公告)号：US20200278908A1
公开(公告)日：2020-09-03
申请号：US16803856
申请日：2020-02-27
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Jongtae Kwak , Aaron P. Boehm
Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.
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公开(公告)号：US20200242057A1
公开(公告)日：2020-07-30
申请号：US16846146
申请日：2020-04-10
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Matthew A. Prather
IPC: G06F13/16 , G06F1/3206 , G06F1/3234 , G06F1/3296 , G06F5/06
Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
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公开(公告)号：US20250157514A1
公开(公告)日：2025-05-15
申请号：US18954321
申请日：2024-11-20
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer , Scott D. Van De Graaff , Mark D. Ingram , Todd Jackson Plum
Abstract: Methods, systems, and devices for memory traffic monitoring are described. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a characteristic related to an operational bias of circuits of the memory device. The memory device may use the characteristic (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.
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公开(公告)号：US12299325B2
公开(公告)日：2025-05-13
申请号：US17464334
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Todd Jackson Plum , Scott D. Van De Graaff , Scott E. Schaefer , Mark D. Ingram
IPC: G06F3/06
Abstract: Methods, systems, and devices for operating frequency monitoring for memory devices are described for monitoring one or more operating frequency ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more operating frequency ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.
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Patent Agency Ranking
公开(公告)号：US12079068B2
公开(公告)日：2024-09-03
申请号：US17889982
申请日：2022-08-17
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
CPC classification number: G06F11/0787 , G06F11/073 , G06F11/0769
Abstract: Methods, systems, and devices for error log indication via error control information are described. For instance, a memory device may transmit, to a host device, a first signal including a set of error control bits indicating that an error log of the memory device includes information for use by the host device. The memory device may receive, from the host device in response to the first signal, a second signal including a request to retrieve the information of the error log. The memory device may transmit, to the host device in response to the second signal, a third signal including the information of the error log.
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公开(公告)号：US12066891B2
公开(公告)日：2024-08-20
申请号：US17820085
申请日：2022-08-16
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
CPC classification number: G06F11/1068 , G06F11/0772 , G11C7/1069
Abstract: Methods, systems, and devices for memory operations are described. A read command may be received at a memory device from a host device. As part of an error control operation, a first set of error control bits may be generated for the set of data. Based on the first set of error control bits, a failure of a matching operation associated with the error control operation may be determined. Based on determining the failure of the matching operation, a second set of error control bits that is different than the first set of error control bits may be transmitted to the host device. The second set of error control bits may indicate that the matching operation failed at the memory device.
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公开(公告)号：US12040037B2
公开(公告)日：2024-07-16
申请号：US17808043
申请日：2022-06-21
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
CPC classification number: G11C29/46 , G11C29/42 , G11C29/4401
Abstract: Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.
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公开(公告)号：US20240220354A1
公开(公告)日：2024-07-04
申请号：US18435710
申请日：2024-02-07
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
CPC classification number: G06F11/0793 , G06F11/073 , G06F11/1048
Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.
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公开(公告)号：US20240211343A1
公开(公告)日：2024-06-27
申请号：US18590671
申请日：2024-02-28
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
CPC classification number: G06F11/1048 , G06F11/0793 , G06F11/1068
Abstract: Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.
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