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公开(公告)号：US06757876B2
公开(公告)日：2004-06-29
申请号：US10064444
申请日：2002-07-15
申请人： Peter A. Habitz
发明人： Peter A. Habitz
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and system for extracting circuit characteristics from a circuit design comprises extracting first cell characteristics from a portion of said circuit design using a first set of environmental conditions. The invention then extracts second cell characteristics from the portion of the circuit design using a second set of environmental conditions. The invention determines a difference between the first cell characteristics and the second cell characteristics and labels a placeability of the portion of the circuit design based on the difference.
摘要翻译： 用于从电路设计中提取电路特性的方法和系统包括使用第一组环境条件从所述电路设计的一部分中提取第一单元特性。 然后，本发明使用第二组环境条件从电路设计的部分中提取第二电池特性。 本发明确定了第一单元特性和第二单元特性之间的差异，并且基于该差来标记电路设计的该部分的可放置性。
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82.发明授权Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing 失效用于通过动态偏置来保持寄生提取的3西格玛过程公差的过程和系统公开(公告)号：US06430729B1
公开(公告)日：2002-08-06
申请号：US09494975
申请日：2000-01-31
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and structure for a method of determining characteristics of parasitic elements in an integrated circuit comprising, identifying manufacturing process parameters of devices in the integrated circuit, calculating a parasitic performance distribution for each of the devices based on the manufacturing process parameters, combining the parasitic performance distribution for each of the devices into a net parasitic value, and forming a parameterized model based on the net parasitic values.
摘要翻译： 一种用于确定集成电路中的寄生元件的特性的方法的方法和结构，包括：识别集成电路中的器件的制造工艺参数，基于制造工艺参数计算每个器件的寄生性能分布，组合寄生 每个器件的性能分布成为净寄生值，并且基于净寄生值形成参数化模型。
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公开(公告)号：US08855993B2
公开(公告)日：2014-10-07
申请号：US13251517
申请日：2011-10-03
申请人： Peter A. Habitz , Amol A. Joshi
发明人： Peter A. Habitz , Amol A. Joshi
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.
摘要翻译： 方法和系统通过将第一值应用于第一变量和第二值到模拟的第二变量来对集成电路设计进行仿真以产生第一矩阵角模拟值。 方法和系统使用不同的值对第一和第二变量重复模拟，以产生第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。 方法和系统创建矩阵，矩阵具有第一矩阵角模拟值，第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。 方法和系统基于矩阵内的现有模拟值来内插矩阵内的所有剩余值。
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84.发明授权Test path selection and test program generation for performance testing integrated circuit chips 有权测试路径选择和测试程序生成用于性能测试集成电路芯片公开(公告)号：US08543966B2
公开(公告)日：2013-09-24
申请号：US13294210
申请日：2011-11-11
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.
摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。
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85.发明申请公开(公告)号：US20130226536A1
公开(公告)日：2013-08-29
申请号：US13406897
申请日：2012-02-28
CPC分类号： G06F17/5036 , G06F17/50 , G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.
摘要翻译： 公开了一种方法，其包括使用在计算机化设备上运行的电路识别引擎来检测集成电路中的数量和类型设备。 该方法通过选择一组主导有源器件并使用该主导有源器件集来执行仿真来表征器件变化。 可以使用三种不同的选项来优化任何电弧/压摆/负载组合的模拟次数。 积极减少使用最少数量的模拟，以牺牲一些精度损失为代价，保守的减少可以减少精确度损失可忽略的模拟次数，动态减少动态地确定给定精度要求所需的最小模拟次数。
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86.发明授权Disposition of integrated circuits using performance sort ring oscillator and performance path testing 有权使用性能分类环形振荡器和性能路径测试对集成电路进行处理公开(公告)号：US08490040B2
公开(公告)日：2013-07-16
申请号：US13294220
申请日：2011-11-11
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译： 一种配置集成电路芯片的方法和系统。 该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。
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87.发明申请TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS 有权性能测试集成电路卡的测试路径选择和测试程序生成公开(公告)号：US20130125073A1
公开(公告)日：2013-05-16
申请号：US13294210
申请日：2011-11-11
IPC分类号： G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths
摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径
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88.发明授权Ring oscillator structure and method of separating random and systematic tolerance values 失效环形振荡器结构和分离随机和系统容差值的方法公开(公告)号：US07266474B2
公开(公告)日：2007-09-04
申请号：US11162197
申请日：2005-08-31
申请人： Peter A. Habitz , Jerry D. Hayes
发明人： Peter A. Habitz , Jerry D. Hayes
CPC分类号： G05B23/0221 , G01R31/2648
摘要： A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic delay effects. The delay distributions are analyzed to isolate the systematic and the random contributions to the standard deviation of the distributions.
摘要翻译： 环形振荡器测试结构包括可在不同数量级之间切换的至少两个重叠环。 测量在不同位置处形成的一组振荡器中的不同数量的级的延迟分布，其受到不同的系统延迟效应的影响。 分析延迟分布，分析系统和随机贡献与分布的标准偏差。
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89.发明授权Method of calculating 3-dimensional fringe characteristics using specially formed extension shapes 失效使用特殊形状的延伸形状计算3维条纹特征的方法公开(公告)号：US06477686B1
公开(公告)日：2002-11-05
申请号：US09560577
申请日：2000-04-27
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A structure and method for performing a capacitance extraction on an integrated circuit, includes determining a parallel-plate capacitance between devices on different levels within the integrated circuit, adding extension shapes around each of the devices, reducing an area of overlapping extension shapes, multiplying a remaining area of the extension shapes by a constant to produce a fringe capacitance; and summing the parallel-plate capacitance and the fringe capacitance.
摘要翻译： 一种用于在集成电路上执行电容提取的结构和方法，包括：确定集成电路内不同级别的器件之间的平行板电容，在每个器件周围增加扩展形状，减少重叠扩展形状的面积，将 延伸形状的剩余面积为常数以产生边缘电容; 并且平行板电容和边缘电容相加。
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公开(公告)号：US06473887B1
公开(公告)日：2002-10-29
申请号：US09560065
申请日：2000-04-27
IPC分类号： G06F945
CPC分类号： G06F17/5036
摘要： A method and structure for performing capacitance extraction during the design of an integrated circuit includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency factor based on the wiring density, calculating a lateral capacitance assuming virtual wires are present in the integrated circuit, and calculating a vertical capacitance based on the transparency factor.
摘要翻译： 在集成电路设计期间进行电容提取的方法和结构包括输入指定的布线密度和设计要求，根据设计要求确定线段的最小间距，根据布线密度计算透明度因子，计算出 在集成电路中存在假想虚线的横向电容，并且基于透明度因子计算垂直电容。
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