公开(公告)号：US5481230A

公开(公告)日：1996-01-02

申请号：US339420

申请日：1994-11-14

Applicant: Paul Chang ,  Dan H. Wolaver ,  J. Howell Mitchell, Jr.

Inventor： Paul Chang ,  Dan H. Wolaver ,  J. Howell Mitchell, Jr.

IPC: G06F1/025 ,  H03C3/00 ,  H03K7/04

CPC classification number: H03C3/00 ,  G06F1/025 ,  H03K7/04

Abstract: A phase modulator circuit and method for generating an output signal having individually positionable edges is described. The phase modulator includes a programmable pulse generator, such as an interval counter, or a delay for producing the output signal, and a control value source, such as a memory, for delivering a sequence of control values to the generator. The control values determine the time between successive output pulses.

Abstract translation: 描述了一种用于产生具有可单独定位的边缘的输出信号的相位调制器电路和方法。 相位调制器包括诸如间隔计数器的可编程脉冲发生器或用于产生输出信号的延迟，以及用于将一系列控制值传递给发生器的控制值源（例如存储器）。 控制值确定连续输出脉冲之间的时间。

公开(公告)号：US4577391A

公开(公告)日：1986-03-25

申请号：US635371

申请日：1984-07-27

Applicant: Steve Hsia ,  Paul Chang

Inventor： Steve Hsia ,  Paul Chang

IPC: H01L27/092 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/32

CPC classification number: H01L21/823864

Abstract: A CMOS semiconductor structure having insulation sidewall spacers whose width is selected independently for NMOS and PMOS devices. The width of the spacer is selected to reduce hot electron injection in the N channel device and to insure that the gate and source regions are aligned with or underlap the gate in the P channel device. A narrower spacer is used for the P channel device than for the N channel device which permits the formation of a P channel device having a threshold voltage less than 1 volt.

Abstract translation: 具有绝缘侧壁间隔物的CMOS半导体结构，其宽度针对NMOS和PMOS器件独立选择。 选择间隔物的宽度以减少N沟道器件中的热电子注入，并确保栅极和源极区域与P沟道器件中的栅极对准或下划线。 对于P沟道器件使用较窄的间隔物，而不是N沟道器件，其允许形成阈值电压小于1伏特的P沟道器件。

公开(公告)号：US11595232B1

公开(公告)日：2023-02-28

申请号：US17373774

申请日：2021-07-13

Applicant: Paul Chang

Inventor： Paul Chang

IPC: H04L12/46

Abstract: A fabric for container virtual machines (CM) has cross fabric spine switches coupled to spine switches, each spine switch coupled to has a leaf switches, each leaf switch coupled to servers hosting CVM processes. Each of the leaf switches has an uplink port coupled to a spine switch leaf port configured in a mesh. The spine switches have a plurality of uplink ports for coupling to a plurality of cross fabric spine (CFS) ports into a mesh. The cross fabric spine switches keep a CF-NHCIB table of entries containing capabilities, and also a CF-FIB slice table which maintains entries for assignment of CVMs to new spine switches, such as GTID range, MAC Range, IP range associated with a spine port and spine address (MAC and/or IP) for transferring packets through the fabric.

公开(公告)号：US09257858B2

公开(公告)日：2016-02-09

申请号：US13371668

申请日：2012-02-13

Applicant: Chio Fai Aglaia Kong ,  Guangmin He ,  Paul Chang

Inventor： Chio Fai Aglaia Kong ,  Guangmin He ,  Paul Chang

IPC: H02J7/06 ,  H02J7/24 ,  H02J7/00 ,  H02J1/08 ,  H04L12/413

CPC classification number: H02J7/0047 ,  H02J1/08 ,  H02J7/0021 ,  H04L12/413

Abstract: A charging circuit and method for charging a power storage device in a power over Ethernet environment are necessary to prevent unnecessary power consumption. Power sourcing equipment continuously supplies power to a connected device after determining that the device is compatible. In order to prevent supply of power after a power storage device attains full charge, a charging circuit may include an interface for supplying electric power; a sensing circuit including a switch in series with a resistor; and a voltage detection circuit. The voltage detection circuit may communicate with the sensing circuit and may output a first signal that turns the switch OFF when the voltage of the power storage device is greater than or equal to a first voltage and may output a second signal that turns the switch ON when the voltage of the power storage device is less than or equal to a second voltage.

Abstract translation: 为了防止不必要的电力消耗，需要在以太网供电环境中对蓄电装置进行充电的充电电路和方法。 电源设备在确定设备兼容后，会连续向连接的设备供电。 为了防止蓄电装置充满电后的电力供给，充电电路可以包括用于供电的接口， 感测电路，包括与电阻器串联的开关; 和电压检测电路。 电压检测电路可以与感测电路通信，并且可以输出当蓄电装置的电压大于或等于第一电压时使开关断开的第一信号，并且可以输出第二信号，其在第 蓄电装置的电压小于或等于第二电压。

公开(公告)号：US08653765B2

公开(公告)日：2014-02-18

申请号：US13194589

申请日：2011-07-29

Applicant: Paul Chang ,  Tsair-Rong Chen ,  Jeen-Sheen Row ,  Chin-Sheng Lu

Inventor： Paul Chang ,  Tsair-Rong Chen ,  Jeen-Sheen Row ,  Chin-Sheng Lu

IPC: H02P1/00

CPC classification number: H02P23/04

Abstract: In a method and module for controlling rotation of a motorized spindle driven by a driving unit, a sensing unit senses vibration of the spindle and generates a voltage signal corresponding to the vibration of the spindle. A processing unit receives the voltage signal from the sensing unit, generates an adjusting ratio equal to a reference voltage corresponding to a predetermined vibration level of the spindle by the voltage signal upon detecting that the voltage signal is greater than the reference voltage and is less than a predetermined threshold voltage that is greater than the reference voltage, and outputs a control signal corresponding to the adjusting ratio to the driving unit such that the driving unit reduces a rotation speed of the spindle by the adjusting ratio in response to the control signal from the processing unit.

Abstract translation: 在用于控制由驱动单元驱动的电动主轴的旋转的方法和模块中，感测单元感测主轴的振动并产生对应于主轴的振动的电压信号。 处理单元从感测单元接收电压信号，当检测到电压信号大于参考电压时，产生等于与主轴的预定振动水平相对应的参考电压的调整比例，并且小于参考电压 大于参考电压的预定阈值电压，并将与调节比相对应的控制信号输出到驱动单元，使得驱动单元响应于来自控制信号的控制信号而减小主轴的转速通过调节比 处理单元。

公开(公告)号：US08554282B2

公开(公告)日：2013-10-08

申请号：US12896007

申请日：2010-10-01

Applicant: Paul Chang

Inventor： Paul Chang

IPC: H04B1/38

CPC classification number: H04M1/7253 ,  G06F3/1454 ,  H04M1/72544 ,  H04N1/33315 ,  H04N1/33376 ,  H04N2201/0086 ,  H04N2201/0089

Abstract: Screen content from a first telecommunication device, such as a smartphone, is cast wirelessly and received by a second telecommunications device. The received screen content is formatted for presentation on the second telecommunications device. Screen content from among the received screen content may be selected for transmitting to a third telecommunications device. The selected screen content is transmitted to the third telecommunications device for presentation on a virtual screen of the third telcommunications device.

Abstract translation: 来自第一电信设备（诸如智能电话）的屏幕内容被无线地投射并由第二电信设备接收。 所接收的屏幕内容被格式化以在第二电信设备上呈现。 可以选择所接收的屏幕内容中的屏幕内容来发送给第三电信设备。 所选择的屏幕内容被发送到第三电信设备，以呈现在第三电话设备的虚拟屏幕上。

公开(公告)号：US08492748B2

公开(公告)日：2013-07-23

申请号：US13169542

申请日：2011-06-27

Applicant: Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

Inventor： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

IPC: H01L29/06 ,  H01L31/00 ,  H01L29/15 ,  H01L51/40

CPC classification number: H01L29/66045 ,  H01L51/055

Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.

Abstract translation: 一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。 一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。 通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。 一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。 然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。 独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。

公开(公告)号：US08429576B2

公开(公告)日：2013-04-23

申请号：US13471789

申请日：2012-05-15

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

公开(公告)号：US08237492B2

公开(公告)日：2012-08-07

申请号：US11618900

申请日：2006-12-31

Applicant: Stephen Chi-Wang Au ,  Arya Behzad ,  Paul Chang

Inventor： Stephen Chi-Wang Au ,  Arya Behzad ,  Paul Chang

IPC: G05F3/02

CPC classification number: H03F3/45475 ,  H03F2203/45048

Abstract: Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.

Abstract translation: 公开了用于在存在IC工艺制造变化的情况下补偿SoC参数的工艺传感器的方法和系统的某些方面。 一种方法的方面可以包括确定与单个集成电路内的至少一个晶体管相关联的工艺变化量。 可以通过利用与工艺相关的电流，带隙电流和与晶体管的当前温度相关联的电流来补偿确定的工艺变化量。 过程相关电流，带隙电流和与晶体管的当前温度相关联的电流可以被组合以产生输出电流。 可以基于产生的输出电流来确定可变电阻器两端产生的电压。

公开(公告)号：US08216902B2

公开(公告)日：2012-07-10

申请号：US12536741

申请日：2009-08-06

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: H01L21/8234

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  Y10S977/938

Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

Abstract translation: 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。