公开(公告)号：US08429576B2

公开(公告)日：2013-04-23

申请号：US13471789

申请日：2012-05-15

申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC分类号： G06F17/50

CPC分类号： G01R31/26 ,  G06F17/5045

摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

公开(公告)号：US08239790B2

公开(公告)日：2012-08-07

申请号：US13216362

申请日：2011-08-24

申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC分类号： G06F17/50

CPC分类号： G01R31/26 ,  G06F17/5045

摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US20120227019A1

公开(公告)日：2012-09-06

申请号：US13471789

申请日：2012-05-15

申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC分类号： G06F17/50

CPC分类号： G01R31/26 ,  G06F17/5045

摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US20110307846A1

公开(公告)日：2011-12-15

申请号：US13216362

申请日：2011-08-24

申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC分类号： G06F17/50

CPC分类号： G01R31/26 ,  G06F17/5045

摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US08042070B2

公开(公告)日：2011-10-18

申请号：US11876853

申请日：2007-10-23

申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC分类号： G06F17/50

CPC分类号： G01R31/26 ,  G06F17/5045

摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US20090106714A1

公开(公告)日：2009-04-23

申请号：US11876853

申请日：2007-10-23

申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC分类号： G06F9/45

CPC分类号： G01R31/26 ,  G06F17/5045

摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US07705345B2

公开(公告)日：2010-04-27

申请号：US10751916

申请日：2004-01-07

申请人： Stephen W. Bedell ,  Kevin K. Chan ,  Dureseti Chidambarrao ,  Silke H. Christianson ,  Jack O. Chu ,  Anthony G. Domenicucci ,  Kam-Leung Lee ,  Anda C. Mocuta ,  John A. Ott ,  Qiqing C. Ouyang

发明人： Stephen W. Bedell ,  Kevin K. Chan ,  Dureseti Chidambarrao ,  Silke H. Christianson ,  Jack O. Chu ,  Anthony G. Domenicucci ,  Kam-Leung Lee ,  Anda C. Mocuta ,  John A. Ott ,  Qiqing C. Ouyang

IPC分类号： H01L29/06 ,  H01L31/072

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

摘要翻译： 应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。 松弛的第一材料和应变的第二材料形成FinFET的鳍。

公开(公告)号：US20080179636A1

公开(公告)日：2008-07-31

申请号：US11307224

申请日：2007-01-27

申请人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta ,  David M. Onsongo ,  Carl J. Radens

发明人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta ,  David M. Onsongo ,  Carl J. Radens

IPC分类号： H01L29/04 ,  H01L21/335 ,  H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7849

摘要： The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.

摘要翻译： 本发明涉及各自包含应变半导体通道的高性能n沟道场效应晶体管（n-FET），以及通过使用包含假象形成的压缩应变的掩埋伪晶层来形成这种n-FET的方法。

公开(公告)号：US07691698B2

公开(公告)日：2010-04-06

申请号：US11358483

申请日：2006-02-21

申请人： Dureseti Chidambarrao ,  Anda C. Mocuta ,  Dan M. Mocuta ,  Carl Radens

发明人： Dureseti Chidambarrao ,  Anda C. Mocuta ,  Dan M. Mocuta ,  Carl Radens

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

摘要翻译： 本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。 在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。 此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

公开(公告)号：US06881635B1

公开(公告)日：2005-04-19

申请号：US10708746

申请日：2004-03-23

申请人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda C. Mocuta ,  Haining S. Yang ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda C. Mocuta ,  Haining S. Yang ,  Huilong Zhu

IPC分类号： C30B25/18 ,  C30B29/06 ,  H01L21/20 ,  H01L21/285 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  C30B23/00 ,  H01L21/36

CPC分类号： H01L29/78696 ,  C30B25/18 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/28562 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78687

摘要： A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.

摘要翻译： 由SiGe层支撑的应变硅层上的平面NFET通过在晶体管本体外部并且在应变硅层下方除去SiGe材料并且利用外延硅替代去除的材料来实现降低的外部电阻，从而为晶体管电极提供较低电阻并允许 更好地控制砷的扩散。