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    Low-power and low-latency device enumeration with cartesian addressing
    81.
    发明授权
    Low-power and low-latency device enumeration with cartesian addressing 有权

    公开(公告)号：US09979782B2

    公开(公告)日：2018-05-22

    申请号：US15077841

    申请日：2016-03-22

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  James Panian ,  Richard Wietfeldt

    IPC: H04L29/08 ,  H04L29/12 ,  G06F13/42

    CPC classification number: H04L67/1091 ,  G06F13/4247 ,  G06F2213/0052 ,  H04L61/2007 ,  H04L61/604

    Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

    RADIO FREQUENCY FRONT END (RFFE) COMMAND CODE EXTENSION WITH UNIFORM SEQUENCE START CONDITION (SSC)
    83.
    发明申请
    RADIO FREQUENCY FRONT END (RFFE) COMMAND CODE EXTENSION WITH UNIFORM SEQUENCE START CONDITION (SSC) 审中-公开

    公开(公告)号：US20180074985A1

    公开(公告)日：2018-03-15

    申请号：US15696567

    申请日：2017-09-06

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Helena Deirdre O'Shea ,  Richard Dominic Wietfeldt

    IPC: G06F13/362 ,  G06F13/42

    CPC classification number: G06F13/362 ,  G06F13/4247 ,  H04L12/40013 ,  H04W84/20

    Abstract: Radio Frequency Front End (RFFE) command code extensions with uniform start sequence condition (SSC) are disclosed. In one aspect, the RFFE protocol reserves one of the remaining reserved command codes as a command code extension command. In a first aspect, use of the command code extension command allows insertion of another command field after an existing command code and before a payload. The command code extension command may include the ability to nest plural command code extension commands providing multiple layers of commands so as to provide necessary and sufficient unused codes for future needs. In a second aspect, the command code extension command may allow a designation of a particular subset of commands to be associated with the command codes in the new command code field. In this aspect, command codes are reused with potentially different meanings based on which subset of commands was indicated.

    TRIPLE-DATA-RATE TECHNIQUE FOR A SYNCHRONOUS LINK
    84.
    发明申请
    TRIPLE-DATA-RATE TECHNIQUE FOR A SYNCHRONOUS LINK 审中-公开

    公开(公告)号：US20180039598A1

    公开(公告)日：2018-02-08

    申请号：US15226113

    申请日：2016-08-02

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Helena Deirdre O'Shea

    IPC: G06F13/42 ,  G06F13/364

    Abstract: Systems, methods, and apparatus for transmitting additional information over a synchronous serial bus are described. A method performed at a transmitting device coupled to the serial bus includes providing first data in a data signal to be transmitted on a first wire of a multi-wire serial bus, providing a series of pulses in a clock signal to be transmitted on a second wire of a multi-wire serial bus, where each pulse has a rising edge and a falling edge, each edge being aligned with a different bit of the first data. The method may include encoding second data in the clock signal by controlling a duration of each pulse in the series of pulses based on a value of one or more bits of the second data, and transmitting the data signal and the clock signal over the serial bus.

    TWO-WIRE LINE-MULTIPLEXED UART TO FOUR-WIRE HIGH-SPEED UART BRIDGING WITH INTEGRATED FLOW CONTROL
    87.
    发明申请
    TWO-WIRE LINE-MULTIPLEXED UART TO FOUR-WIRE HIGH-SPEED UART BRIDGING WITH INTEGRATED FLOW CONTROL 审中-公开

    公开(公告)号：US20170329737A1

    公开(公告)日：2017-11-16

    申请号：US15151682

    申请日：2016-05-11

    Applicant: QUALCOMM Incorporated

    Inventor： Nitinkumar Barot ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F13/362

    CPC classification number: G06F13/4282 ,  G06F13/362 ,  G06F13/405

    Abstract: Systems, methods, and apparatus for bridging between different types of serial interface are disclosed. A method performed by a bridge circuit includes synchronizing transmissions on a 4-wire serial interface with transmissions on a 2-wire serial interface when a stop bit is detected on data lines of at least one interface, receiving a first clear-to-send notification from a first wire of the 2-wire serial interface, asserting a request-to-send signal on a first flow-control line of the 4-wire serial interface, receiving data bits from a first data line of the 4-wire serial interface while the request-to-send signal is asserted, and transmitting the data bits on the first wire of the 2-wire serial interface after receiving the first clear-to-send notification.

    PRIORITY-BASED DATA COMMUNICATION OVER MULTIPLE COMMUNICATION BUSES
    88.
    发明申请
    PRIORITY-BASED DATA COMMUNICATION OVER MULTIPLE COMMUNICATION BUSES 有权

    公开(公告)号：US20170212850A1

    公开(公告)日：2017-07-27

    申请号：US15002558

    申请日：2016-01-21

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

    IPC: G06F13/18 ,  G06F13/364 ,  G06F13/42 ,  H04L12/40

    CPC classification number: G06F13/18 ,  G06F12/1425 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4282 ,  H04L12/40143 ,  H04L12/40182 ,  H04L12/403

    Abstract: Priority-based data communication over multiple communication buses is disclosed. In this regard, an electronic device is communicatively coupled to a first communication bus and a second communication bus. The electronic device is configured to detect communication signals communicated over the first communication bus and the second communication bus. If the communication signals are detected on both the first communication bus and the second communication bus, the electronic device is further configured to protect data received over the second communication bus from being overwritten by data received over the first communication bus. By configuring the electronic device to support multiple communication buses, it is possible to configure one of the multiple communication buses as a priority communication bus, thus allowing time-critical communications to be carried out over the priority communication bus in a timely manner without preempting ongoing communications on other communication buses.

    FULL-MASK PARTIAL-BIT-FIELD (FM-PBF) TECHNIQUE FOR LATENCY SENSITIVE MASKED-WRITE
    89.
    发明申请
    FULL-MASK PARTIAL-BIT-FIELD (FM-PBF) TECHNIQUE FOR LATENCY SENSITIVE MASKED-WRITE 有权

    公开(公告)号：US20170147521A1

    公开(公告)日：2017-05-25

    申请号：US15346602

    申请日：2016-11-08

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Wietfeldt ,  Helena Deirdre O'Shea

    IPC: G06F13/362 ,  G06F9/30

    CPC classification number: G06F13/362 ,  G06F9/30101 ,  G06F13/38

    Abstract: Systems, methods, and apparatus for data communication are provided. An apparatus maybe configured to generate a mask field in a packet to be transmitted through an interface to a slave device, the mask field having a first number of bits, provide a control-bit field in the packet, the control-bit field having a second number of bits, where the second number of bits is less than the first number of bits, and transmit the packet through the interface. The packet may be addressed to a control register of the slave device. The control register may have the first number of bits. Each bit in the control-bit field may correspond to a bit of the control register that is identified by the mask field.

    INPUT/OUTPUT SIGNAL BRIDGING AND VIRTUALIZATION IN A MULTI-NODE NETWORK
    90.
    发明申请
    INPUT/OUTPUT SIGNAL BRIDGING AND VIRTUALIZATION IN A MULTI-NODE NETWORK 审中-公开
    多节点网络中的输入/输出信号桥接和虚拟化

    公开(公告)号：US20170075852A1

    公开(公告)日：2017-03-16

    申请号：US15242368

    申请日：2016-08-19

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Radu Pitigoi-Aron

    IPC: G06F13/42 ,  G06F15/17 ,  G06F13/40 ,  G06F15/177

    CPC classification number: G06F13/4282 ,  G06F13/385 ,  G06F13/4022 ,  G06F15/17 ,  G06F15/177

    Abstract: In an aspect, an integrated circuit obtains a set of general purpose input/output (GPIO) signals for one or more peripheral devices, obtains a first virtual GPIO packet that includes the set of GPIO signals independent of a central processing unit, and transmits the first virtual GPIO packet to the one or more peripheral devices over an I3C bus independent of the central processing unit. The integrated circuit may further obtain a set of configuration signals for configuring one or more GPIO pins of the one or more peripheral devices, obtain a second virtual GPIO packet that includes the set of configuration signals independent of the central processing unit, and transmit the second virtual GPIO packet to the one or more peripheral devices over the I3C bus independent of the central processing unit.

    Abstract translation: 一方面，集成电路获得用于一个或多个外围设备的一组通用输入/输出（GPIO）信号，获得独立于中央处理单元的包括一组GPIO信号的第一虚拟GPIO分组，并发送 第一个虚拟GPIO数据包通过独立于中央处理单元的I3C总线上的一个或多个外设。 集成电路还可以获得用于配置一个或多个外围设备的一个或多个GPIO引脚的一组配置信号，获得包括独立于中央处理单元的一组配置信号的第二虚拟GPIO分组，并且发送第二个 虚拟GPIO数据包到I3C总线上的一个或多个外设，独立于中央处理器。

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