公开(公告)号：US07800945B2

公开(公告)日：2010-09-21

申请号：US12138371

申请日：2008-06-12

申请人： Raul-Adrian Cernea

发明人： Raul-Adrian Cernea

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.

摘要翻译： 在非易失性存储器中，使用多通道索引编程方法将一组存储器单元分别编程到其目标状态，这减少了验证步骤的数量。 对于每个单元，程序索引保持存储施加到单元的最后编程电压。 在第一次编程过程中，每个单元都应用一系列增量编程脉冲进行索引。 第一个编程通过之后是验证和一个或多个后续编程传递，以修剪对各个目标状态的任何短暂的下降。 如果单元无法验证到其目标状态，则其程序索引增加，并允许通过来自最后接收的脉冲的下一个脉冲对单元进行编程。 重复验证和编程遍历，直到组中的所有单元格被验证到其各自的目标状态。 不需要脉冲之间的验证操作。

公开(公告)号：US07715235B2

公开(公告)日：2010-05-11

申请号：US12197955

申请日：2008-08-25

申请人： Raul-Adrian Cernea

发明人： Raul-Adrian Cernea

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C2211/5621

摘要： A ramp-down programming voltage is used to program a group of nonvolatile memory cells in parallel, step by step from a highest step to a lowest step. Overall programming time is improved when a conventional setup for program inhibit together with a verify after each program step are avoided. A program voltage estimate is provided for each cell indicating the programming voltage expected to program the cell to its target. Initially, all but those cells having estimates at or above the current program voltage step will be program-inhibited. Thereafter, with each descending program voltage step, additional cells will be un-inhibited. Once un-inhibited, a cell need not be re-inhibited even if programmed to its target. This is because subsequent program steps are at lower voltages and ineffective in programming the cell beyond its target. The un-inhibit operation in one implementation amounts to simply pulling the associated bit lines to ground.

摘要翻译： 使用斜坡编程电压来并行地编程一组非易失性存储器单元，从最高级到最低级逐步地编程。 当避免在每个程序步骤之后的程序禁止的常规设置以及验证时，总体编程时间得到改善。 为每个单元提供了一个程序电压估计，指示预期将该单元编程到其目标的编程电压。 最初，除了那些具有或高于当前编程电压阶跃的估计的单元格将被程序禁止。 此后，通过每个降序编程电压步骤，附加单元将被禁止。 一旦未被禁止，即使编程到其目标，单元不需要被重新禁止。 这是因为后续的程序步骤处于较低的电压，并且将单元编程超出其目标无效。 在一个实现中的禁止操作相当简单地将相关联的位线拉到地。

公开(公告)号：US07643348B2

公开(公告)日：2010-01-05

申请号：US11733694

申请日：2007-04-10

申请人： Raul-Adrian Cernea

发明人： Raul-Adrian Cernea

IPC分类号： G11C16/04

CPC分类号： G11C8/10 ,  G11C11/5628

摘要： In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. The checkpoint is an actual programming voltage that programs the memory cell in question to a verified designated threshold voltage level.

摘要翻译： 在具有存储器单元阵列的非易失性存储器中，其中存储器单元可单独地编程为阈值电压电平范围中的一个，提供预测编程模式，其中预定功能预测需要应用什么编程电压电平 为了将给定的存储器单元编程到给定的目标阈值电压电平。 以这种方式，不需要执行验证操作，从而大大提高了编程操作的性能。 在优选实施例中，预定功能是线性的，并且通过一个或多个检查点在编程时针对每个存储器单元进行校准。 检查点是将所讨论的存储器单元编程到经验证的指定阈值电压电平的实际编程电压。

公开(公告)号：US20090310419A1

公开(公告)日：2009-12-17

申请号：US12138378

申请日：2008-06-12

申请人： Raul-Adrian Cernea

发明人： Raul-Adrian Cernea

IPC分类号： G11C11/34

CPC分类号： G11C16/3459 ,  G11C16/3454

摘要： In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.

摘要翻译： 在非易失性存储器中，使用多通道索引编程方法将一组存储器单元分别编程到其目标状态，这减少了验证步骤的数量。 对于每个单元，程序索引保持存储施加到单元的最后编程电压。 在第一次编程过程中，每个单元都应用一系列增量编程脉冲进行索引。 第一个编程通过之后是验证和一个或多个后续编程传递，以修剪对各个目标状态的任何短暂的下降。 如果单元无法验证到其目标状态，则其程序索引增加，并允许通过来自最后接收的脉冲的下一个脉冲对单元进行编程。 重复验证和编程遍历，直到组中的所有单元格被验证到其各自的目标状态。 不需要脉冲之间的验证操作。

公开(公告)号：US20090310418A1

公开(公告)日：2009-12-17

申请号：US12138371

申请日：2008-06-12

申请人： Raul-Adrian Cernea

发明人： Raul-Adrian Cernea

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.

摘要翻译： 在非易失性存储器中，使用多通道索引编程方法将一组存储器单元分别编程到其目标状态，这减少了验证步骤的数量。 对于每个单元，程序索引保持存储施加到单元的最后编程电压。 在第一次编程过程中，每个单元都应用一系列增量编程脉冲进行索引。 第一个编程通过之后是验证和一个或多个后续编程传递，以修剪对各个目标状态的任何短暂的下降。 如果单元无法验证到其目标状态，则其程序索引增加，并允许通过来自最后接收的脉冲的下一个脉冲对单元进行编程。 重复验证和编程遍历，直到组中的所有单元格被验证到其各自的目标状态。 不需要脉冲之间的验证操作。

公开(公告)号：US07447070B2

公开(公告)日：2008-11-04

申请号：US11422719

申请日：2006-06-07

申请人： Raul-Adrian Cernea

发明人： Raul-Adrian Cernea

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C16/26

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits among each stack are factored out. In one aspect, a serial bus allows communication between components in each stack, thereby reducing the number of connections in a stack to a minimum. A bus controller sends control and timing signals to control the operation of the components and their interactions through the serial bus. In a preferred embodiment, the bus transactions of corresponding components in all the similar stacks are controlled simultaneously.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 每个堆栈中的冗余电路被分解出来。 在一个方面，串行总线允许每个堆栈中的组件之间的通信，从而将堆叠中的连接数减少到最小。 总线控制器发送控制和定时信号，以通过串行总线控制组件的操作及其相互作用。 在优选实施例中，同时控制所有类似堆栈中相应组件的总线事务。

公开(公告)号：US20080266957A1

公开(公告)日：2008-10-30

申请号：US12163017

申请日：2008-06-27

申请人： Farookh Moogat ,  Raul-Adrian Cernea ,  Shou-Chang Tsao ,  Tai-Yuan Tseng

发明人： Farookh Moogat ,  Raul-Adrian Cernea ,  Shou-Chang Tsao ,  Tai-Yuan Tseng

IPC分类号： G11C16/06

CPC分类号： G11C29/846

摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

摘要翻译： 存储器在其用户部分中的缺陷位置可由冗余部分中的冗余位置替换。 用户和冗余部分中的数据锁存器允许从或被写入存储器的数据与数据总线交换。 缺陷位置锁存冗余方案假定包括有缺陷列的数据锁存器的列电路仍然可用。 用于缺陷列的数据锁存器用于缓冲通常可从冗余部分中的数据锁存器访问的相应冗余数据。 以这种方式，用户和冗余数据可从用户数据锁存器获得，并且流数据进出数据总线被简化和性能提高。

公开(公告)号：US20080158983A1

公开(公告)日：2008-07-03

申请号：US11617981

申请日：2006-12-29

申请人： Nima Mokhlesi ,  Raul-Adrian Cernea

发明人： Nima Mokhlesi ,  Raul-Adrian Cernea

IPC分类号： G11C16/28

CPC分类号： G11C16/3418

摘要： When reading data from a non-volatile storage element that is part of a group of connected non-volatile storage elements, resistance information is measured for the group. One or more read parameters are set based on the measured resistance information. The read process is then performed using the one or more parameters.

摘要翻译： 当从作为一组连接的非易失性存储元件的一部分的非易失性存储元件读取数据时，测量该组的电阻信息。 基于所测量的电阻信息设置一个或多个读取参数。 然后使用一个或多个参数执行读取过程。

公开(公告)号：US20080137419A1

公开(公告)日：2008-06-12

申请号：US12019564

申请日：2008-01-24

申请人： Raul-Adrian Cernea

发明人： Raul-Adrian Cernea

IPC分类号： G11C16/06

CPC分类号： G11C29/846 ,  G11C29/808 ,  Y10T70/7655

摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits.

摘要翻译： 存储器在其用户部分中的缺陷位置可由冗余部分中的冗余位置替换。 在用户和冗余部分的列电路中的数据锁存允许从或被写入存储器的数据与数据总线交换。 远程冗余方案具有从任何数量的列电路可访问的中央缓冲器可用的冗余数据。 冗余数据缓冲电路可以实现总线与来自用户数据锁存器的数据的交换，除了从中央缓冲区获取数据时，缺陷位置除外。 以这种方式，仅用于用户部分的寻址用于总线交换。 此外，冗余数据的可访问性不会受到列电路相对于冗余数据锁存器的位置的限制，并且缓冲的冗余数据可以以比由列电路施加的细的粒度访问。

公开(公告)号：US07379346B2

公开(公告)日：2008-05-27

申请号：US11223055

申请日：2005-09-08

申请人： Khandker N. Quader ,  Raul-Adrian Cernea

发明人： Khandker N. Quader ,  Raul-Adrian Cernea

IPC分类号： G11C11/03

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3418

摘要： A non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process are presented. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. This can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.

摘要翻译： 提出了一种用于其操作的非易失性存储器和方法，其可以在擦除处理期间减少未选择的单元的干扰量。 对于在公共阱结构上形成的一组存储元件，所有字线最初都以相同的高电压擦除信号充电，以确保阱和字线之间没有净电压差。 所选择的字线然后放电到地，而未选择的字线和阱保持在高电压。 这可以在不增加任何音调区域电路或在存储器阵列中添加新的线以及在最小额外的外围区域的情况下实现。 优点包括在未选择的存储元件中较少的电位擦除干扰以及所选元件的更严格的擦除分布。