公开(公告)号：US20140029357A1

公开(公告)日：2014-01-30

申请号：US13559377

申请日：2012-07-26

申请人： Dana Lee ,  Yi-Chieh Chen ,  Farookh Moogat

发明人： Dana Lee ,  Yi-Chieh Chen ,  Farookh Moogat

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C16/30

摘要： A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.

摘要翻译： 具有多个存储器骰子的非易失性存储器管理同时操作，以便不超过系统功率容量。 负载信号总线以与系统功率容量成比例的强度被拉高。 每个模具具有一个驱动器，用于将总线的数量下降一定量，与模具状态机所估计的功率需求量相对应。 因此，总线提供负载信号，用作系统功率容量和单个骰子的累积负载之间的仲裁。 因此，当不超过系统功率容量时，负载信号处于高电平状态; 否则处于低状态。 当模具希望执行操作并请求一定量的电力时，它相应地驱动总线，并且其状态机根据负载信号进行操作。

公开(公告)号：US07450426B2

公开(公告)日：2008-11-11

申请号：US11548267

申请日：2006-10-10

申请人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

发明人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3481

摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

摘要翻译： 与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。 当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。 施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。 在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。 在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程，在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，增量值可以增加 同时页面。

公开(公告)号：US07394690B2

公开(公告)日：2008-07-01

申请号：US11389655

申请日：2006-03-24

申请人： Farookh Moogat ,  Raul-Adrian Cernea ,  Shouchang Tsao ,  Tai-Yuan Tseng

发明人： Farookh Moogat ,  Raul-Adrian Cernea ,  Shouchang Tsao ,  Tai-Yuan Tseng

IPC分类号： G11C16/06

CPC分类号： G11C29/846

摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

摘要翻译： 存储器在其用户部分中的缺陷位置可由冗余部分中的冗余位置替换。 用户和冗余部分中的数据锁存器允许从或被写入存储器的数据与数据总线交换。 缺陷位置锁存冗余方案假定包括有缺陷列的数据锁存器的列电路仍然可用。 用于缺陷列的数据锁存器用于缓冲通常可从冗余部分中的数据锁存器访问的相应冗余数据。 以这种方式，用户和冗余数据可从用户数据锁存器获得，并且流数据进出数据总线被简化和性能提高。

公开(公告)号：US20070245065A1

公开(公告)日：2007-10-18

申请号：US11379910

申请日：2006-04-24

申请人： Yishai Kagan ,  Rizwan Ahmed ,  Farookh Moogat

发明人： Yishai Kagan ,  Rizwan Ahmed ,  Farookh Moogat

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C16/102 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/4099

摘要： A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

摘要翻译： 公开了一种包括闪速存储器件和控制器的闪速存储器系统，其可根据高级数据传输模式操作。 闪存器件可以在“传统”模式下操作，其中读取数据由存储器与来自控制器的读取数据选通的每个周期同步地呈现，并且其中输入数据由存储器与每个周期同步地锁存 从控制器写入数据选通脉冲。 在控制器将启动命令转发到存储器的高级模式中，闪速存储器本身来源于读取数据选通信号，同时与该读取数据选通信号的下降沿和上升沿同时呈现数据。 在高级模式下，输入数据由写入数据选通的两个边沿同步显示。 数据和控制信号的电压摆幅从常规标准中减少，以降低功耗。

公开(公告)号：US20080158968A1

公开(公告)日：2008-07-03

申请号：US11618482

申请日：2006-12-29

申请人： Farookh Moogat ,  Teruhiko Kamei

发明人： Farookh Moogat ,  Teruhiko Kamei

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

摘要： A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string are particularly susceptible to errors due to program disturb. An adaptive memory-state partitioning scheme is employed to overcome the errors, in which each memory cells are generally partitioned to store multiple bits of data, except for the ones adjacent both ends where relatively less bits are stored. In this way, the storage of relatively less bits in the memory cells adjacent both ends of a NAND string affords sufficient margin to overcome the errors. For example, in a memory designed to store 2-bit data, the cells adjacent both ends of a NAND string would each be configured to store one bit of the 2-bit data.

摘要翻译： NAND型闪速存储器被组织成NAND串，其中每个是串联的存储器单元串，并且通过串的两端的选择晶体管连接到位线或源极线。 与NAND串相邻的存储单元特别容易受到程序干扰的错误的影响。 采用自适应存储器状态分割方案来克服错误，其中每个存储器单元通常被分割以存储多个数据位，除了存储相对较少位的相邻两端的数据。 以这种方式，在与NAND串的两端相邻的存储单元中相对较少位的存储提供足够的余量以克服错误。 例如，在设计用于存储2位数据的存储器中，与NAND串的两端相邻的单元每个都被配置为存储2位数据的一位。

公开(公告)号：US20080084752A1

公开(公告)日：2008-04-10

申请号：US11548267

申请日：2006-10-10

申请人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

发明人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3481

摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

摘要翻译： 与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。 当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。 施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。 在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。 在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程，在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，增量值可以增加 同时页面。

公开(公告)号：US07313023B2

公开(公告)日：2007-12-25

申请号：US11078173

申请日：2005-03-11

申请人： Yan Li ,  Farookh Moogat

发明人： Yan Li ,  Farookh Moogat

IPC分类号： G11C7/18 ,  G11C8/12 ,  G11C7/02

CPC分类号： G11C7/18 ,  G11C16/0483 ,  G11C16/24 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit lines and a bottom set of sense amps control the odd bit lines. The segmentation transistors turn on or off depending on the selected word line location in the array. Since bit line capacitance is mainly from the metal bit line to bit line coupling to their immediate neighbors, the bit line neighbors in the partitioned array are floating in some segments of the bit lines. The overall bit line capacitance is significantly reduced with a negligible increase in die size, resulting in reduced sensing times and enhanced read and write performance.

摘要翻译： 通过可切换地划分阵列中的位线来分割N个段中的存储器阵列的本发明。 在示例性实施例中，顶部的一组感测放大器控制偶数位线，并且底部的一组感测放大器控制奇数位线。 根据阵列中选定的字线位置，分割晶体管导通或关断。 由于位线电容主要是从金属位线到位线耦合到它们的直接邻居，所以分割阵列中的位线相邻部分浮动在位线的某些段中。 总体位线电容显着降低，管芯尺寸增加可以忽略不计，从而减少了传感时间，提高了读写性能。

公开(公告)号：US08924626B2

公开(公告)日：2014-12-30

申请号：US12770358

申请日：2010-04-29

申请人： Steven S. Cheng ,  Dennis Ea ,  Jianmin Huang ,  Alexander Kwok-Tung Mak ,  Farookh Moogat

发明人： Steven S. Cheng ,  Dennis Ea ,  Jianmin Huang ,  Alexander Kwok-Tung Mak ,  Farookh Moogat

IPC分类号： G06F12/00 ,  G06F1/24

CPC分类号： G06F1/24

摘要： A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold.

摘要翻译： 公开了一种用于阶段性强力密集型操作的方法和系统。 非易失性存储设备控制器检测电源复位。 控制器与非易失性存储设备中的非易失性存储器通信。 响应于检测到电源复位，控制器确定复位非易失性存储设备中的非易失性存储器所需的电流消耗。 当确定的电流消耗小于电流消耗阈值时，控制器同时复位所有非易失性存储器。 如果确定的电流消耗大于当前消耗阈值，则控制器复位多个非易失性存储器的第一子集，并且在预定延迟之后，复位非易失性存储器的第二子集。 因此，通过将操作划分成不超过阈值的一系列步骤，可以不超过电流消耗阈值来执行功率密集型操作。

公开(公告)号：US07663950B2

公开(公告)日：2010-02-16

申请号：US12163017

申请日：2008-06-27

申请人： Farookh Moogat ,  Raul-Adrian Cernea ,  Shou-Chang Tsao ,  Tai-Yuan Tseng

发明人： Farookh Moogat ,  Raul-Adrian Cernea ,  Shou-Chang Tsao ,  Tai-Yuan Tseng

IPC分类号： G11C29/00 ,  G11C7/10

CPC分类号： G11C29/846

摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

摘要翻译： 存储器在其用户部分中的缺陷位置可由冗余部分中的冗余位置替换。 用户和冗余部分中的数据锁存器允许从或被写入存储器的数据与数据总线交换。 缺陷位置锁存冗余方案假定包括有缺陷列的数据锁存器的列电路仍然可用。 用于缺陷列的数据锁存器用于缓冲通常可从冗余部分中的数据锁存器访问的相应冗余数据。 以这种方式，用户和冗余数据可从用户数据锁存器获得，并且流数据进出数据总线被简化和性能提高。

公开(公告)号：US07474561B2

公开(公告)日：2009-01-06

申请号：US11548264

申请日：2006-10-10

申请人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

发明人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3481

摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

摘要翻译： 与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。 当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。 施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。 在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。 在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程，在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，增量值可以增加 同时页面。