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    Propagating data using mirrored lock caches
    81.
    发明申请
    Propagating data using mirrored lock caches 失效
    使用镜像锁高速缓存传播数据

    公开(公告)号：US20070150665A1

    公开(公告)日：2007-06-28

    申请号：US11315465

    申请日：2005-12-22

    申请人： Ravi Arimilli ,  Rama Govindaraju ,  Peter Hochschild ,  Bruce Mealey ,  Satya Sharma ,  Balaram Sinharoy

    发明人： Ravi Arimilli ,  Rama Govindaraju ,  Peter Hochschild ,  Bruce Mealey ,  Satya Sharma ,  Balaram Sinharoy

    IPC分类号： G06F12/14 ,  G06F12/16

    CPC分类号： G06F12/0806 ,  G06F9/526 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2097 ,  G06F12/0815 ,  G06F12/0875

    摘要： A method, processing node, and computer readable medium for propagating data using mirrored lock caches are disclosed. The method includes coupling a first mirrored lock cache associated with a first processing node to a bus that is communicatively coupled to at least a second mirrored lock cache associated with a second processing node in a multi-processing system. The method further includes receiving, by the first mirrored lock cache, data from a processing node. The data is then mirrored automatically so that the same data is available locally at the second mirrored lock cache for use by the second processing node.

    摘要翻译： 公开了一种用于使用镜像锁高速缓存传播数据的方法，处理节点和计算机可读介质。 该方法包括将与第一处理节点相关联的第一镜像锁缓存耦合到通信地耦合到与多处理系统中的第二处理节点相关联的至少第二镜像锁高速缓存的总线。 该方法还包括由第一镜像锁高速缓存从处理节点接收数据。 然后自动镜像数据，以便相同的数据在第二个镜像锁缓存器本地可用，供第二个处理节点使用。

    Methods and arrangements to manage on-chip memory to reduce memory latency
    82.
    发明申请
    Methods and arrangements to manage on-chip memory to reduce memory latency 有权
    管理片上存储器以减少内存延迟的方法和安排

    公开(公告)号：US20060155886A1

    公开(公告)日：2006-07-13

    申请号：US11032876

    申请日：2005-01-11

    申请人： Dilma da Silva ,  Elmootazbellah Elnozahy ,  Orran Krieger ,  Hazim Shafi ,  Xiaowei Shen ,  Balaram Sinharoy ,  Robert Tremaine

    发明人： Dilma da Silva ,  Elmootazbellah Elnozahy ,  Orran Krieger ,  Hazim Shafi ,  Xiaowei Shen ,  Balaram Sinharoy ,  Robert Tremaine

    IPC分类号： G06F3/00

    CPC分类号： G06F12/08 ,  G06F12/0893 ,  G06F2212/251 ,  G06F2212/253

    摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

    摘要翻译： 考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。 许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。 因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。 几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

    Circuits, systems and methods for performing branch predictions by selectively accessing bimodal and fetch-based history tables
    83.
    发明授权
    Circuits, systems and methods for performing branch predictions by selectively accessing bimodal and fetch-based history tables 失效
    通过有选择地访问双峰和基于获取的历史表来执行分支预测的电路，系统和方法

    公开(公告)号：US06976157B1

    公开(公告)日：2005-12-13

    申请号：US09435070

    申请日：1999-11-04

    申请人： Balaram Sinharoy

    发明人： Balaram Sinharoy

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3806 ,  G06F9/3848

    摘要： Branch prediction circuitry including a bimodal branch history table, a fetch-based branch history table and a selector table is provided. The local branch history table includes a plurality of entries each for storing a prediction value and accessed by selected bits of a branch address. The fetch-based branch history table included a plurality of entries for storing a prediction value and accessed by a pointer generated from selected bits of the branch address and bits from a history register. The selector table includes a plurality of entries each for storing a selection bit and accessed by a pointer generated from selected bits from the branch address and bits from the history register, each selector bit is used for selecting between a prediction value accessed from the local history table and a prediction value accessed from the fetch-based history table.

    摘要翻译： 提供了包括双模分支历史表，基于获取的分支历史表和选择表的分支预测电路。 本地分支历史表包括多个条目，每个条目用于存储预测值，并由分支地址的选定位访问。 基于获取的分支历史表包括用于存储预测值的多个条目，并且由从分支地址的选定位产生的指针和来自历史寄存器的位进行访问的条目。 选择器表包括多个条目，每个条目用于存储选择位，并由从分支地址的选定位产生的指针和来自历史寄存器的位进行访问，每个选择器位用于在从本地历史访问的预测值之间进行选择 表和从基于获取的历史表访问的预测值。

    Method and apparatus for capturing event traces for debug and analysis
    84.
    发明授权
    Method and apparatus for capturing event traces for debug and analysis 失效
    捕获事件跟踪的方法和装置，用于调试和分析

    公开(公告)号：US06961875B2

    公开(公告)日：2005-11-01

    申请号：US09815548

    申请日：2001-03-22

    申请人： Michael Stephen Floyd ,  Balaram Sinharoy

    发明人： Michael Stephen Floyd ,  Balaram Sinharoy

    IPC分类号： G06F9/44 ,  G06F11/00 ,  G06F11/36

    CPC分类号： G06F11/3636

    摘要： A trace array having M entries with corresponding M addresses is used to store the states of input signals. The M addresses of the trace array are sequenced with a counter that counts a clock beginning at a starting count and counting to an ending count. If the ending count is exceeded, the counter starts over at the starting count. The counter outputs are decoded to addresses of the trace array. An event signal is generated on the occurrence of an operation of interest and the counter is started and stopped in response to sequences of the event signals, thus starting and stopping the recording of states of the input signals in the trace array. When an error or particular condition signal occurs, traces corresponding to the input signals are saved in the trace array. A start signal enables tracing and event logic generates event sequence signals which alternately start and stop the recording of traces. The event sequences are programmed by inputs to enable guaranteed statistical chances of capturing states of the input signals corresponding to a particular event signal occurring before an error or another event signal.

    摘要翻译： 使用具有对应M地址的M个条目的跟踪数组来存储输入信号的状态。 跟踪数组的M地址用计数器计数，该计数器从起始计数开始计数一个时钟，并计数到结束计数。 如果超出结束计数，则计数器从起始计数开始。 计数器输出被解码为跟踪数组的地址。 在感兴趣的操作的发生时产生事件信号，并且响应于事件信号的序列开始和停止计数器，从而启动和停止跟踪阵列中的输入信号的状态的记录。 当发生错误或特定条件信号时，对应于输入信号的迹线将保存在跟踪数组中。 起始信号使跟踪和事件逻辑产生交替地启动和停止记录记录的事件序列信号。 事件序列由输入编程，以使保证的统计机会能够捕捉与在错误或其它事件信号之前发生的特定事件信号相对应的输入信号的状态。

    Software hint to improve the branch target prediction accuracy
    85.
    发明授权
    Software hint to improve the branch target prediction accuracy 失效
    软件提示提高分支目标预测精度

    公开(公告)号：US06823447B2

    公开(公告)日：2004-11-23

    申请号：US09798166

    申请日：2001-03-01

    申请人： Robert William Hay ,  Balaram Sinharoy

    发明人： Robert William Hay ,  Balaram Sinharoy

    IPC分类号： G06F900

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3846

    摘要： A field is defined in branch instructions which is interpreted by software as “Hint” bits and these bits are used to signal the processor of special circumstances that may arise when doing speculative branch instruction execution to enable better branch address prediction accuracy and a reduction in link stack corruption which improves overall execution times. A programmer or compiler determines if a branch instruction usage fits in the context for a Hint action. If so, the compiler or programmer, using assembly/machine language, sets Hint bits in the branch instruction when it is compiled. If the branch is later speculatively executed, the processor decodes the Hint bits and executes and a hardware action corresponding the decode of the Hint bits. These Hints include four specific Hint actions, however, the field reserved for Hint bits is five bit wide reserving up to thirty-two specific Hint cases may be specified. These Hint cases (or Hint bits) may be interpreted differently for each type of branch instruction supported.

    摘要翻译： 在分支指令中定义了一个字段，由软件将其解释为“提示”位，这些位用于向处理器发出信号，以便在进行推测性分支指令执行时可能出现的特殊情况，以实现更好的分支地址预测精度和减少链路 堆栈损坏可以提高整体执行时间。 程序员或编译器确定分支指令使用是否符合提示操作的上下文。 如果是这样，编译器或程序员使用汇编/机器语言在编译时在转移指令中设置提示位。 如果分支稍后被推测执行，则处理器对提示位进行解码并执行和与提示位的解码相对应的硬件动作。 这些提示包括四个具体的提示操作，但是，为提示位保留的字段是五位宽保留，最多可以指定三十二个特定的提示情况。 对于支持的每种类型的分支指令，可以对这些提示情况（或提示位）进行不同的解释。

    Increasing the overall prediction accuracy for multi-cycle branch prediction and apparatus by enabling quick recovery
    86.
    发明授权
    Increasing the overall prediction accuracy for multi-cycle branch prediction and apparatus by enabling quick recovery 有权
    通过实现快速恢复，提高多周期分支预测和设备的总体预测精度

    公开(公告)号：US06598152B1

    公开(公告)日：2003-07-22

    申请号：US09436264

    申请日：1999-11-08

    申请人： Balaram Sinharoy

    发明人： Balaram Sinharoy

    IPC分类号： G06F938

    CPC分类号： G06F9/3861 ,  G06F9/3848

    摘要： Enables a processor to quickly recover reliable use of a multi-cycle index used in a branch prediction mechanism for certain types of flush events occurring in the processor pipeline, whether the flush event occurs for a non-branch instruction or for a branch instruction contained in the same dispatch group. A GHV (global history vector) value is used in the generation of a multi-cycle index required for locating a prediction in a GBHT (global branch history table) for the instruction associated with the GHV value. The GHV value is captured in a BIQ (branch information queue) element representing each branch instruction selected for execution of a program. The BIQ element also captures an associated GHV count when the GHV value is captured. Recovery involves quickly restoring a GHV register to the captured GHV value when the GHV count captured in the same BIQ element has at least the value of N where N is the number contiguous fetch cycles without interruption required for the development of a steady state multi-cycle index value used in locating branch predictions in a global branch history table.

    摘要翻译： 使处理器可以快速恢复在分支预测机制中使用的多循环索引的可靠使用，用于在处理器流水线中发生的某些类型的刷新事件，无论是否为非分支指令或分支指令发生刷新事件 相同的调度组。 GHV（全局历史向量）值用于生成与GHV值相关联的指令的GBHT（全局分支历史表）中的预测所需的多周期索引。 GHV值被捕获在表示为执行程序而选择的每个分支指令的BIQ（分支信息队列）元素中。 当捕获GHV值时，BIQ元素还捕获相关的GHV计数。 恢复涉及当在同一BIQ元件中捕获的GHV计数至少具有N值N时，快速将GHV寄存器恢复到所捕获的GHV值，其中N是连续获取周期数，而不需要中断开发稳态多周期 用于在全局分支历史表中定位分支预测的索引值。

    Apparatus and method for accessing a memory device during speculative instruction branching
    87.
    发明授权
    Apparatus and method for accessing a memory device during speculative instruction branching 失效
    在推测性指令分支期间访问存储器件的装置和方法

    公开(公告)号：US06526503B1

    公开(公告)日：2003-02-25

    申请号：US09434763

    申请日：1999-11-04

    申请人： Balaram Sinharoy

    发明人： Balaram Sinharoy

    IPC分类号： G06F942

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3863 ,  G06F9/4486

    摘要： Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address for accessing a corresponding instruction in a memory device. A counter generates a pointer to an entry in an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks. Selector circuitry selects the active one of the logical stacks in accordance with the performance of the Push and Pop operations.

    摘要翻译： 指令分支电路，其包括多个逻辑堆栈，每个逻辑堆栈具有多个条目，用于存储访问存储器设备中相应指令的地址。 计数器产生指向逻辑堆栈中的活动的一个条目中的条目的指针，该计数器包括递增逻辑，其在按压操作之后增加存储的指针值，并且在弹出操作之后将存储的指针值递减到逻辑的活动的一个之后的递减逻辑 堆栈 选择器电路根据Push和Pop操作的性能选择活动的逻辑堆栈。

    Assist thread for injecting cache memory in a microprocessor
    89.
    发明授权
    Assist thread for injecting cache memory in a microprocessor 有权
    协助在微处理器中注入高速缓存的线程

    公开(公告)号：US08949837B2

    公开(公告)日：2015-02-03

    申请号：US13434423

    申请日：2012-03-29

    申请人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

    发明人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

    IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F9/38 ,  G06F12/08 ,  G06F9/48

    CPC分类号： G06F9/383 ,  G06F9/3851 ,  G06F9/4881 ,  G06F12/0862

    摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

    摘要翻译： 数据处理系统包括具有访问多级缓存存储器的微处理器。 微处理器执行从源代码对象编译的主线程。 该系统包括用于执行也源自源代码对象的辅助线程的处理器。 辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。 配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。 辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。