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    Propagating data using mirrored lock caches
    2.
    发明申请
    Propagating data using mirrored lock caches 失效
    使用镜像锁高速缓存传播数据

    公开(公告)号：US20070150665A1

    公开(公告)日：2007-06-28

    申请号：US11315465

    申请日：2005-12-22

    申请人： Ravi Arimilli ,  Rama Govindaraju ,  Peter Hochschild ,  Bruce Mealey ,  Satya Sharma ,  Balaram Sinharoy

    发明人： Ravi Arimilli ,  Rama Govindaraju ,  Peter Hochschild ,  Bruce Mealey ,  Satya Sharma ,  Balaram Sinharoy

    IPC分类号： G06F12/14 ,  G06F12/16

    CPC分类号： G06F12/0806 ,  G06F9/526 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2097 ,  G06F12/0815 ,  G06F12/0875

    摘要： A method, processing node, and computer readable medium for propagating data using mirrored lock caches are disclosed. The method includes coupling a first mirrored lock cache associated with a first processing node to a bus that is communicatively coupled to at least a second mirrored lock cache associated with a second processing node in a multi-processing system. The method further includes receiving, by the first mirrored lock cache, data from a processing node. The data is then mirrored automatically so that the same data is available locally at the second mirrored lock cache for use by the second processing node.

    摘要翻译： 公开了一种用于使用镜像锁高速缓存传播数据的方法，处理节点和计算机可读介质。 该方法包括将与第一处理节点相关联的第一镜像锁缓存耦合到通信地耦合到与多处理系统中的第二处理节点相关联的至少第二镜像锁高速缓存的总线。 该方法还包括由第一镜像锁高速缓存从处理节点接收数据。 然后自动镜像数据，以便相同的数据在第二个镜像锁缓存器本地可用，供第二个处理节点使用。

    Efficient and flexible memory copy operation
    3.
    发明申请
    Efficient and flexible memory copy operation 失效
    高效灵活的内存复制操作

    公开(公告)号：US20070150676A1

    公开(公告)日：2007-06-28

    申请号：US11316663

    申请日：2005-12-22

    申请人： Ravi Arimilli ,  Rama Govindaraju ,  Peter Hochschild ,  Bruce Mealey ,  Satya Sharma ,  Balaram Sinharoy

    发明人： Ravi Arimilli ,  Rama Govindaraju ,  Peter Hochschild ,  Bruce Mealey ,  Satya Sharma ,  Balaram Sinharoy

    IPC分类号： G06F12/16

    CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/3824

    摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.

    摘要翻译： 公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。 该方法包括在处理器中接收对半同步存储器复制操作的呼叫。 半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。 该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。 存储器复制操作被放置在队列中以由存储器控制器执行。 队列耦合到存储器控制器。 随着随后的指令从指令流水线可用，继续执行至少一个后续指令。

    Validity of address ranges used in semi-synchronous memory copy operations
    4.
    发明申请
    Validity of address ranges used in semi-synchronous memory copy operations 有权
    在半同步存储器复制操作中使用的地址范围的有效性

    公开(公告)号：US20070150675A1

    公开(公告)日：2007-06-28

    申请号：US11315757

    申请日：2005-12-22

    申请人： Ravi Arimilli ,  Rama Govindaraju ,  Peter Hochschild ,  Bruce Mealey ,  Satya Sharma ,  Balaram Sinharoy

    发明人： Ravi Arimilli ,  Rama Govindaraju ,  Peter Hochschild ,  Bruce Mealey ,  Satya Sharma ,  Balaram Sinharoy

    IPC分类号： G06F12/16

    CPC分类号： G06F12/1441 ,  G06F12/0888 ,  G06F12/0897

    摘要： A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.

    摘要翻译： 公开了一种用于保护存储器页面的内容的系统，方法和可读取的计算机。 该方法包括确定半同步存储器复制操作的开始。 确定正在执行半同步存储器复制操作的地址范围。 检测到发出的删除页表条目的指令。 所述方法还包括确定所发出的指令是否旨在去除与地址范围中的至少一个地址相关联的页表条目。 响应于发出的指令旨在去除页表条目，所发出的指令的执行停止，直到半同步存储器复制操作完成。

    Method and system for managing cache injection in a multiprocessor system
    5.
    发明申请
    Method and system for managing cache injection in a multiprocessor system 有权
    在多处理器系统中管理缓存注入的方法和系统

    公开(公告)号：US20060064518A1

    公开(公告)日：2006-03-23

    申请号：US10948407

    申请日：2004-09-23

    申请人： Patrick Bohrer ,  Ahmed Gheith ,  Peter Hochschild ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  Balaram Sinharoy

    发明人： Patrick Bohrer ,  Ahmed Gheith ,  Peter Hochschild ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  Balaram Sinharoy

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.

    摘要翻译： 用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。 该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。 可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。 或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。 在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

    Thread partitioning in a multi-core environment
    6.
    发明授权
    Thread partitioning in a multi-core environment 有权
    多核环境中的线程分区

    公开(公告)号：US08707016B2

    公开(公告)日：2014-04-22

    申请号：US12024211

    申请日：2008-02-01

    申请人： Ravi K. Arimilli ,  Juan C. Rubio ,  Balaram Sinharoy

    发明人： Ravi K. Arimilli ,  Juan C. Rubio ,  Balaram Sinharoy

    IPC分类号： G06F9/30

    CPC分类号： G06F9/4843 ,  G06F9/3851

    摘要： A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to common instruction boundaries. As a first partition in the set of main thread binaries executes within a first core, a second partition in the set of helper thread binaries executes within a second core, thus “warming up” the cache in the second core. When the first partition of the main completes execution, a second partition of the main core moves to the second core, and executes using the warmed up cache in the second core.

    摘要翻译： 创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。 辅助线程二进制文件集和主线程二进制文件集合根据公共指令边界进行分区。 作为主线程二进制文件集合中的第一分区在第一核心内执行，该辅助线程二进制文件集中的第二分区在第二核心内执行，从而“预热”第二核心中的高速缓存。 当主要的第一分区完成执行时，主核心的第二分区移动到第二核心，并使用第二核心中的预热高速缓存执行。

    Hardware assist thread for dynamic performance profiling
    7.
    发明授权
    Hardware assist thread for dynamic performance profiling 失效
    用于动态性能分析的硬件辅助线

    公开(公告)号：US08612730B2

    公开(公告)日：2013-12-17

    申请号：US12796124

    申请日：2010-06-08

    申请人： Ronald P. Hall ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Balaram Sinharoy ,  Zhong Liang Wang

    发明人： Ronald P. Hall ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Balaram Sinharoy ,  Zhong Liang Wang

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/327 ,  G06F11/3466 ,  G06F2201/865 ,  G06F2201/88

    摘要： A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.

    摘要翻译： 一种用于管理程序中的指令的运行的方法和数据处理系统。 数据处理系统的处理器接收监视单元的监视指令。 处理器确定一组辅助线程的至少一个辅助线程是否可用作辅助线程。 响应于确定所述一组次要线程的至少一个辅助线程可用作辅助线程，所述处理器从所述辅助线程组中选择所述至少一个辅助线程以成为所述辅助线程。 处理器将程序中指令的运行情况从主线程更改为辅助线程。

    Speculative popcount data creation
    8.
    发明授权
    Speculative popcount data creation 有权
    投机性的popcount数据创建

    公开(公告)号：US08387065B2

    公开(公告)日：2013-02-26

    申请号：US12425343

    申请日：2009-04-16

    申请人： Ravi K. Arimilli ,  Ronald N. Kalla ,  Balaram Sinharoy

    发明人： Ravi K. Arimilli ,  Ronald N. Kalla ,  Balaram Sinharoy

    IPC分类号： G06F9/46 ,  G06F9/45 ,  G06F9/30 ,  G06F9/40

    CPC分类号： G06F9/3001 ,  G06F9/30018 ,  G06F9/3842

    摘要： A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth of real time processing. The method comprises: identifying data to be stored to memory for which a popcount may need to be determined; speculatively performing a popcount operation on the data as a background process of the processor while the data is being stored to memory; storing the data to a first memory location; and storing a value of the popcount generated by the popcount operation within a second memory location. The method further comprises: determining a size of data; determining a granular level at which the popcount operation on the data will be performed; and reserving a size of said second memory location that is sufficiently large to hold the value of the popcount.

    摘要翻译： 一种方法和数据处理系统，通过该方法和数据处理系统有效地执行人口计数（popcount）操作，而不会导致关键处理周期的延迟和丢失以及实时处理的带宽。 该方法包括：识别要存储到可能需要确定一个弹出窗口的存储器的数据; 在将数据存储到存储器中的情况下，作为处理器的后台处理推测性地对数据进行弹出数据操作; 将数据存储到第一存储器位置; 以及将由所述popcount操作生成的所述popcount的值存储在第二存储器位置内。 该方法还包括：确定数据的大小; 确定将执行对数据的弹出数据操作的粒度级别; 以及保留所述第二存储器位置的大小足够大以保持所述用户名的值。

    Block driven computation with an address generation accelerator
    10.
    发明授权
    Block driven computation with an address generation accelerator 失效
    使用地址生成加速器进行块驱动计算

    公开(公告)号：US08285971B2

    公开(公告)日：2012-10-09

    申请号：US12336315

    申请日：2008-12-16

    申请人： Ravi K. Arimilli ,  Balaram Sinharoy

    发明人： Ravi K. Arimilli ,  Balaram Sinharoy

    IPC分类号： G06F12/00

    CPC分类号： G06F9/383 ,  G06F9/30094 ,  G06F9/345

    摘要： A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.

    摘要翻译： 处理器包括执行指令的至少一个执行单元，耦合到所述至少一个执行单元的至少一个寄存器文件，其缓冲由所述至少一个执行单元访问的操作数，指令排序单元，其通过 所述至少一个执行单元和地址生成加速器。 地址产生加速器响应于从指令排序单元接收的发起信号，计算并输出操作的操作数的第一和第二有效地址。