公开(公告)号：US20120302014A1

公开(公告)日：2012-11-29

申请号：US13384215

申请日：2011-07-04

申请人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

发明人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L21/76289 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772

摘要： A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.

摘要翻译： 提供了一种制造具有空气侧壁的环形栅极硅纳米线晶体管的方法。 该方法与CMOS工艺兼容; 引入的空气侧壁可以有效地减小寄生电容并增加器件的瞬态响应特性，从而适用于高性能逻辑电路。

公开(公告)号：US20120267700A1

公开(公告)日：2012-10-25

申请号：US13255087

申请日：2011-05-26

申请人： Ru Huang ,  Zhan Zhan ,  Qianqian Huang ,  Yangyuan Wang

发明人： Ru Huang ,  Zhan Zhan ,  Qianqian Huang ,  Yangyuan Wang

IPC分类号： H01L29/788

CPC分类号： H01L29/7391

摘要： The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device.

摘要翻译： 本发明公开了一种隧道电流放大晶体管，其涉及CMOS超大规模半导体集成电路（ULSI）中的场效应晶体管逻辑器件的面积。 隧道电流放大晶体管包括半导体衬底，栅极电介质层，发射极，漏极，浮动隧道基极和控制栅极，其中漏极，浮动隧道基极和控制栅极形成传统的TFET结构， 发射极的掺杂类型与浮动隧道基体的掺杂类型相反。 发射极的位置相对于漏极在浮动基底的另一侧。 发射极和浮动隧道基底之间的半导体类型与浮动隧道基底的相同。 与常规TFET相比，本发明的隧道电流放大晶体管可以有效地增加器件的导通电流，并提高器件的驱动能力。

公开(公告)号：US20120243313A1

公开(公告)日：2012-09-27

申请号：US13146005

申请日：2011-04-21

申请人： Yimao Cai ,  Ru Huang ,  Poren Tang ,  Shiqiang Qin

发明人： Yimao Cai ,  Ru Huang ,  Poren Tang ,  Shiqiang Qin

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7885 ,  H01L29/792

摘要： The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.

摘要翻译： 本发明提供一种闪存阵列结构及其编程方法，涉及超大规模集成电路制造技术中非易失性存储器的技术领域。 本发明的闪速存储器阵列包括连接到存储单元的存储单元，字线和位线，其中连接到存储单元的控制栅极的字线和连接到存储单元的漏极端子的位线不垂直 相互交叉但彼此成角度; 沿两个位线之间的通道方向彼此相邻的两个存储单元的控制栅极分别由两个字线控制，其漏极端分别由两个位线控制，并且其源极端子被共享。 本发明还提供了一种用于编程闪存阵列结构的方法，其可以实现具有低功耗的编程。

公开(公告)号：US20120238097A1

公开(公告)日：2012-09-20

申请号：US13513852

申请日：2011-09-29

申请人： Ru Huang ,  Shuangshuang Pu ,  Yujie Ai ,  Zhihua Hao ,  Runsheng Wang

发明人： Ru Huang ,  Shuangshuang Pu ,  Yujie Ai ,  Zhihua Hao ,  Runsheng Wang

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  B82Y30/00 ,  B82Y40/00 ,  H01L28/20

摘要： Disclosed herein is a method for fabricating a fine line, which belongs to a field of ultra-large-scale integrated circuit manufacturing technology. In the invention, three trimming mask processes are performed to effectively improve a profile of the line and greatly reduce the LER (line edge roughness) of the line. At the same time, the invention is combined with a sidewall process, so that a nano-scaled fine line can be successfully fabricated and precisely controlled to 20 nm. Thus, a nano-scaled line with an optimized LER can be fabricated over the substrate.

摘要翻译： 这里公开了一种属于超大规模集成电路制造技术领域的细线的制造方法。 在本发明中，执行三个修整掩模处理以有效地改善线的轮廓并大大降低线的LER（线边缘粗糙度）。 同时，本发明与侧壁工艺相结合，可以成功制作纳米级细线，精确控制为20nm。 因此，可以在衬底上制造具有优化的LER的纳米级线。

公开(公告)号：US20120188821A1

公开(公告)日：2012-07-26

申请号：US13499596

申请日：2011-10-14

申请人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Yu Tang ,  Shenghu Tan ,  Xin Huang ,  Yue Pan

发明人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Yu Tang ,  Shenghu Tan ,  Xin Huang ,  Yue Pan

IPC分类号： G11C16/34

CPC分类号： H01L29/42352 ,  G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

摘要： The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.

摘要翻译： 本发明公开了一种通过使用具有分割沟槽栅的闪存来实现四位存储的方法。 具有分割沟槽栅的闪速存储器在中国专利No.200710105964.2中公开。 在两个沟槽中的每一个与沟道接触的一侧，通过使用沟道热电子注入方法实现电子编程; 并且在另一侧，两个沟槽中的每一个与源极或漏极接触，通过使用FN注入方法来实现电子编程，使得通过改变器件的四位存储器的功能来实现 一种编程模式。 因此，提高了存储密度的装置的性能。

公开(公告)号：US20120187976A1

公开(公告)日：2012-07-26

申请号：US13382415

申请日：2011-09-29

申请人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

发明人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

IPC分类号： G01R31/26

CPC分类号： H01L22/14 ,  G01R31/2621 ,  G01R31/2642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges. After that, the following steps are repeated sequentially to form a loop by changing the bias settings: 1) carriers flow into the channel through the source and the drain to form an inversion layer, and a portion of carriers are confined by the traps in the gate dielectric layer; 2) carriers of the inversion layer flow back to the source and the drain respectively, whereas the carriers confined by the traps in the gate dielectric layer do not flow back to the channel; 3) carriers confined by the traps in the gate dielectric layer flow out through the drain terminal only; and the trap density of the gate dielectric layer are calculated according to the period of the loop, the size of the channel of the device, and DC currents at the source and the drain. The method is simple and effective and is easy to setup the instruments with a low cost. The method is applicable to be used in testing traps in the gate dielectric layer of the devices that have no substrate contact, especially the surrounding-gate device.

摘要翻译： 本发明提供了一种在没有衬底接触的半导体器件的栅介质层中测试阱密度的方法。 器件的源极和漏极是双向对称的，连接到源极和漏极的测试仪器的探头和电缆是双边对称的。 首先，控制栅极，源极和漏极处的偏置设置，使得器件处于不形成反型层的初始状态，并且栅极电介质层中的陷阱对电荷没有施加约束效应。 之后，顺序重复以下步骤，通过改变偏置设置来形成一个环路：1）载流子通过源极和漏极流入沟道，形成一个反型层，一部分载流子被陷阱限制在 栅介质层; 2）反转层的载流子分别流回到源极和漏极，而由栅极电介质层中的陷阱限制的载流子不流回到沟道; 3）由栅极电介质层中的陷阱限制的载流子仅通过漏极端子流出; 并且根据环路的周期，器件的通道的尺寸以及源极和漏极处的直流电流来计算栅极介电层的陷阱密度。 该方法简单有效，易于以低成本设置仪器。 该方法适用于在不与衬底接触的器件的栅极电介质层中测试陷阱，特别是周围栅极器件。

公开(公告)号：US20120113726A1

公开(公告)日：2012-05-10

申请号：US13321120

申请日：2011-03-07

申请人： Ru Huang ,  Yimao Cai ,  Shiqiang Qin ,  Qianqian Huang ,  Poren Tang ,  Yu Tang ,  Gengyu Yang

发明人： Ru Huang ,  Yimao Cai ,  Shiqiang Qin ,  Qianqian Huang ,  Poren Tang ,  Yu Tang ,  Gengyu Yang

IPC分类号： G11C16/26 ,  H01L21/336 ,  H01L27/115

CPC分类号： H01L27/11556 ,  H01L29/7391 ,  H01L29/7889 ,  H01L29/8616

摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.

摘要翻译： 本发明公开了一种闪存及其制作方法及其操作方法。 闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。 在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。 整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。 与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

公开(公告)号：US20060141025A1

公开(公告)日：2006-06-29

申请号：US11284111

申请日：2005-11-21

申请人： Ru Huang ,  Richard Park ,  Chih-Chuan Chang ,  Yu-Chuan Liang ,  David Mold ,  Elaine Lin ,  Jonathan Heller ,  Neil Frazer

发明人： Ru Huang ,  Richard Park ,  Chih-Chuan Chang ,  Yu-Chuan Liang ,  David Mold ,  Elaine Lin ,  Jonathan Heller ,  Neil Frazer

IPC分类号： A61K9/48 ,  A61K31/24 ,  A61K31/205

CPC分类号： A61K9/5153 ,  A61K9/0019 ,  A61K9/0024 ,  A61K9/0043 ,  A61K9/0078 ,  A61K9/1075 ,  A61K9/1271 ,  A61K31/205 ,  A61K31/24

摘要： The present invention provides kits, methods and compositions for the treatment of tumor and other proliferative diseases such as tumors. The compositions herein contain a substantially pure preparation of at least one catecholic butane, including, for example, NDGA compounds in a pharmaceutically acceptable carrier or excipient. The catecholic butane such as NDGA or its derivatives are administered to one or more subjects in need of treatment by a route other than direct injection into the affected tissues or topical application on affected tissues.

摘要翻译： 本发明提供用于治疗肿瘤和其它增殖性疾病如肿瘤的试剂盒，方法和组合物。 本文的组合物含有至少一种儿茶酚丁烷的基本上纯的制剂，包括例如药学上可接受的载体或赋形剂中的NDGA化合物。 将诸如NDGA或其衍生物的儿茶酚丁烷通过除了直接注射到受影响组织内的途径或受影响组织上的局部施用而施用于需要治疗的一个或多个受试者。