公开(公告)号：US08942036B2

公开(公告)日：2015-01-27

申请号：US13499596

申请日：2011-10-14

申请人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Yu Tang ,  Shenghu Tan ,  Xin Huang ,  Yue Pan

发明人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Yu Tang ,  Shenghu Tan ,  Xin Huang ,  Yue Pan

IPC分类号： G11C11/40 ,  H01L29/423 ,  G11C16/04 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42352 ,  G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

摘要： The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.

摘要翻译： 本发明公开了一种通过使用具有分割沟槽栅的闪存来实现四位存储的方法。 具有分割沟槽栅的闪速存储器在中国专利No.200710105964.2中公开。 在两个沟槽中的每一个与沟道接触的一侧，通过使用沟道热电子注入方法实现电子编程; 并且在另一侧，两个沟槽中的每一个与源极或漏极接触，通过使用FN注入方法来实现电子编程，使得通过改变器件的四位存储器的功能来实现 一种编程模式。 因此，提高了存储密度的装置的性能。

公开(公告)号：US20120188821A1

公开(公告)日：2012-07-26

申请号：US13499596

申请日：2011-10-14

申请人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Yu Tang ,  Shenghu Tan ,  Xin Huang ,  Yue Pan

发明人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Yu Tang ,  Shenghu Tan ,  Xin Huang ,  Yue Pan

IPC分类号： G11C16/34

CPC分类号： H01L29/42352 ,  G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

摘要： The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.

摘要翻译： 本发明公开了一种通过使用具有分割沟槽栅的闪存来实现四位存储的方法。 具有分割沟槽栅的闪速存储器在中国专利No.200710105964.2中公开。 在两个沟槽中的每一个与沟道接触的一侧，通过使用沟道热电子注入方法实现电子编程; 并且在另一侧，两个沟槽中的每一个与源极或漏极接触，通过使用FN注入方法来实现电子编程，使得通过改变器件的四位存储器的功能来实现 一种编程模式。 因此，提高了存储密度的装置的性能。

公开(公告)号：US20140145139A1

公开(公告)日：2014-05-29

申请号：US13581470

申请日：2012-02-22

申请人： Ru Huang ,  Yu Tang ,  Yimao Cai ,  Lijie Zhang ,  Gengyu Yang ,  Shenghu Tan ,  Yue Pan ,  Poren Tang

发明人： Ru Huang ,  Yu Tang ,  Yimao Cai ,  Lijie Zhang ,  Gengyu Yang ,  Shenghu Tan ,  Yue Pan ,  Poren Tang

IPC分类号： H01L45/00

CPC分类号： H01L45/149 ,  H01L45/1675 ,  H01L51/0591

摘要： The present invention discloses a transparent flexible resistive memory and a fabrication method thereof. The transparent flexible resistive memory includes a transparent flexible substrate, a memory unit with a MIM capacitor structure over the substrate, wherein a bottom electrode and a top electrode of the memory unit are transparent and flexible, and an intermediate resistive layer is a transparent flexible film of poly(p-xylylene). Poly(p-xylylene) has excellent resistive characteristics. In the device, the substrate, the electrodes and the intermediate resistive layer are all formed of transparent flexible material so that a completely transparent flexible resistive memory which can be used in a transparent flexible electronic system is obtained.

摘要翻译： 本发明公开了一种透明柔性电阻式存储器及其制造方法。 透明柔性电阻存储器包括透明柔性衬底，在衬底上具有MIM电容器结构的存储单元，其中存储单元的底电极和顶电极是透明和柔性的，中间电阻层是透明柔性膜 的聚（对二甲苯）。 聚（对二甲苯）具有优异的电阻特性。 在该器件中，衬底，电极和中间电阻层均由透明柔性材料形成，从而获得可用于透明柔性电子系统中的完全透明的柔性电阻性存储器。

公开(公告)号：US20120261740A1

公开(公告)日：2012-10-18

申请号：US13389720

申请日：2011-10-14

申请人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Shenghu Tan

发明人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Shenghu Tan

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7391 ,  H01L27/1203 ,  H01L29/788 ,  H01L29/8616

摘要： The present invention discloses a flash memory and a method for fabricating the same, and relates to the technical field of the semiconductor memory. The flash memory includes a buried oxygen layer on which a source terminal, a channel, and a drain terminal are disposed, wherein the channel is between the source terminal and the drain terminal, and a tunneling oxide layer, a polysilicon floating gate, a blocking oxide layer, and a polysilicon control gate are sequentially disposed on the channel, and a thin silicon nitride layer is disposed between the source terminal and the channel. The method includes: 1) performing a shallow trench isolation on a SOI silicon substrate to form an active region; 2) sequentially forming a tunneling oxide layer and a first polysilicon layer on the SOI silicon substrate to form a polysilicon floating gate, and forming a blocking oxide layer and a second polysilicon layer to form a polysilicon control gate; 3) etching the resultant structure to form a gate stack structure; 4) forming a drain terminal at one side of the gate stack structure, etching the silicon film at the other side of the gate stack structure, growing a thin silicon nitride layer, and then refilling the hole structure with silicon material, to form a source terminal. The method has the advantages of high programming efficiency, low power consumption, effectively preventing source-drain punchthrough effect.

摘要翻译： 本发明公开了一种闪速存储器及其制造方法，涉及半导体存储器的技术领域。 闪速存储器包括掩埋氧层，其上设置有源极端子，沟道和漏极端子，其中沟道位于源极端子和漏极端子之间，以及隧道氧化物层，多晶硅浮动栅极，阻塞层 氧化物层和多晶硅控制栅极依次设置在沟道上，并且在源极端子和沟道之间设置有薄的氮化硅层。 该方法包括：1）在SOI硅衬底上进行浅沟槽隔离以形成有源区; 2）在SOI硅衬底上依次形成隧道氧化物层和第一多晶硅层，以形成多晶硅浮栅，并形成阻挡氧化层和第二多晶硅层以形成多晶硅控制栅极; 3）蚀刻所得结构以形成栅叠层结构; 4）在栅极堆叠结构的一侧形成漏极端子，蚀刻栅极叠层结构的另一侧的硅膜，生长薄的氮化硅层，然后用硅材料再填充孔结构，以形成源极 终奌站。 该方法具有编程效率高，功耗低，有效防止源极漏极穿通效应的优点。

公开(公告)号：US08526242B2

公开(公告)日：2013-09-03

申请号：US13321120

申请日：2011-03-07

申请人： Ru Huang ,  Yimao Cai ,  Shiqiang Qin ,  Qianqian Huang ,  Poren Tang ,  Yu Tang ,  Gengyu Yang

发明人： Ru Huang ,  Yimao Cai ,  Shiqiang Qin ,  Qianqian Huang ,  Poren Tang ,  Yu Tang ,  Gengyu Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/11556 ,  H01L29/7391 ,  H01L29/7889 ,  H01L29/8616

摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.

摘要翻译： 本发明公开了一种闪存及其制作方法及其操作方法。 闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。 在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。 整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。 与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

公开(公告)号：US20120061637A1

公开(公告)日：2012-03-15

申请号：US13131601

申请日：2011-04-01

申请人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  LIjie Zhang ,  Yu Tang

发明人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  LIjie Zhang ,  Yu Tang

IPC分类号： H01L45/00

CPC分类号： H01L27/249 ,  H01L27/0688 ,  H01L27/101 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1691

摘要： The present invention relates to a field of nonvolatile memory technology in ULSI circuits manufacturing technology and discloses a 3D-structured resistive-switching memory array and a method for fabricating the same. The 3D-structured resistive-switching memory array according to the invention includes a substrate and a stack structure of bottom electrodes/isolation dielectric layers, deep trenches are etched in the stack structure of the bottom electrodes/the isolation dielectric layers; a resistive-switching material layer and a top electrode layer are deposited on sidewalls of the deep trenches, wherein the top electrodes and the bottom electrodes are crossed over each other on the sidewalls of the deep trenches with the resistive-switching material being interposed at cross-over points, each of the cross-over points forms one resistive-switching memory cell, and all of the resistive-switching memory cells form the 3D-structured resistive-switching memory array, and the 3D resistive-switching memory in the array are isolated by the isolation dielectric layers. According to the invention, the storage density of a resistive-switching memory can be improved, the process can be simplified, and the cost of the process can be reduced.

摘要翻译： 本发明涉及ULSI电路制造技术中的非易失性存储器技术领域，并公开了一种3D结构的电阻式开关存储器阵列及其制造方法。 根据本发明的3D结构的电阻式开关存储器阵列包括底部和底部电极/隔离电介质层的堆叠结构，在底部电极/隔离电介质层的堆叠结构中蚀刻深沟槽; 电阻切换材料层和顶部电极层沉积在深沟槽的侧壁上，其中顶部电极和底部电极在深沟槽的侧壁上彼此交叉，电阻切换材料插入在交叉 通过点，每个交叉点形成一个电阻式开关存储单元，并且所有的电阻式开关存储单元形成三维结构的电阻式开关存储器阵列，阵列中的3D电阻式切换存储器是 通过隔离绝缘层隔离。 根据本发明，能够提高电阻式切换存储器的存储密度，能够简化处理，能够降低处理成本。

公开(公告)号：US20120113726A1

公开(公告)日：2012-05-10

申请号：US13321120

申请日：2011-03-07

申请人： Ru Huang ,  Yimao Cai ,  Shiqiang Qin ,  Qianqian Huang ,  Poren Tang ,  Yu Tang ,  Gengyu Yang

发明人： Ru Huang ,  Yimao Cai ,  Shiqiang Qin ,  Qianqian Huang ,  Poren Tang ,  Yu Tang ,  Gengyu Yang

IPC分类号： G11C16/26 ,  H01L21/336 ,  H01L27/115

CPC分类号： H01L27/11556 ,  H01L29/7391 ,  H01L29/7889 ,  H01L29/8616

摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.

摘要翻译： 本发明公开了一种闪存及其制作方法及其操作方法。 闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。 在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。 整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。 与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

公开(公告)号：US08633465B2

公开(公告)日：2014-01-21

申请号：US13513155

申请日：2012-02-08

申请人： Ru Huang ,  Gengyu Yang ,  Yimao Cai ,  Yu Tang ,  Lijie Zhang ,  Yue Pan ,  Shenghu Tan ,  Yinglong Huang

发明人： Ru Huang ,  Gengyu Yang ,  Yimao Cai ,  Yu Tang ,  Lijie Zhang ,  Yue Pan ,  Shenghu Tan ,  Yinglong Huang

IPC分类号： H01L47/00

CPC分类号： H01L45/08 ,  G11C11/5685 ,  G11C13/0007 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146

摘要： The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.

摘要翻译： 本发明公开了一种具有大存储容量的多电平电阻存储器，属于电阻式存储器的制造技术领域。 电阻性存储器包括顶电极和底电极，以及插入在顶电极和底电极之间的多个开关层和有缺陷层的组合，其中，顶电极和底电极分别与开关层 （诸如Ta 2 O 5，TiO 2，HfO 2的膜）和缺陷层（诸如Ti，Au，Ag的金属膜）介于切换层之间。 通过使用本发明，可以提高电阻式存储器的存储容量。

公开(公告)号：US20130069031A1

公开(公告)日：2013-03-21

申请号：US13513155

申请日：2012-02-08

申请人： Ru Huang ,  Gengyu Yang ,  Yimao Cai ,  Yu Tang ,  Lijie Zhang ,  Yue Pan ,  Shenghu Tan ,  Yinglong Huang

发明人： Ru Huang ,  Gengyu Yang ,  Yimao Cai ,  Yu Tang ,  Lijie Zhang ,  Yue Pan ,  Shenghu Tan ,  Yinglong Huang

IPC分类号： H01L45/00

CPC分类号： H01L45/08 ,  G11C11/5685 ,  G11C13/0007 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146

摘要： The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.

摘要翻译： 本发明公开了一种具有大存储容量的多电平电阻存储器，属于电阻式存储器的制造技术领域。 电阻性存储器包括顶电极和底电极，以及插入在顶电极和底电极之间的多个开关层和有缺陷层的组合，其中，顶电极和底电极分别与开关层 （诸如Ta 2 O 5，TiO 2，HfO 2的膜）和缺陷层（诸如Ti，Au，Ag的金属膜）介于切换层之间。 通过使用本发明，可以提高电阻式存储器的存储容量。

公开(公告)号：US20130217199A1

公开(公告)日：2013-08-22

申请号：US13580952

申请日：2012-04-16

申请人： Ru Huang ,  Shenghu Tan ,  Lijie Zhang ,  Yue Pan ,  Yinglong Huang ,  Gengyu Yang ,  Yu Tang ,  Jun Mao ,  Yimao Cai

发明人： Ru Huang ,  Shenghu Tan ,  Lijie Zhang ,  Yue Pan ,  Yinglong Huang ,  Gengyu Yang ,  Yu Tang ,  Jun Mao ,  Yimao Cai

IPC分类号： H01L21/02

CPC分类号： H01L45/04 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2213/15 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

摘要： The present invention discloses a method for fabricating a resistive memory, including: fabricating a bottom electrode over a substrate; partially oxidizing a metal of the bottom electrode through dry-oxygen oxidation or wet-oxygen oxidation to form a metal oxide with a thickness of 3 nm to 50 nm as a resistive material layer; finally fabricating a top electrode over the resistive material layer. The present invention omits a step of depositing a resistive material layer in a conventional method, so as to greatly reduce the process complexity. Meanwhile, a self alignment between the resistive material layer and the bottom electrode can be realized. A full isolation between devices may be ensured so as to obviate the parasite effects occurred in the conventional process methods. Meanwhile, the actual area and designed area of the device are ensured to be consistent.

摘要翻译： 本发明公开了一种制造电阻式存储器的方法，包括：在衬底上制造底电极; 通过干氧氧化或湿氧氧化部分氧化底部电极的金属，形成厚度为3nm至50nm的金属氧化物作为电阻材料层; 最后在电阻材料层上制造顶部电极。 本发明省略了以常规方法沉积电阻材料层的步骤，从而大大降低了工艺的复杂性。 同时，可以实现电阻材料层和底部电极之间的自对准。 可以确保器件之间的完全隔离，以便消除常规工艺方法中发生的寄生效应。 同时，确保设备的实际面积和设计面积一致。