公开(公告)号：US10732866B2

公开(公告)日：2020-08-04

申请号：US15595887

申请日：2017-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Shuangchen Li ,  Bob Brennan ,  Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F3/06 ,  G11C11/4096 ,  G06F15/78

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

公开(公告)号：US20200097417A1

公开(公告)日：2020-03-26

申请号：US16194219

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng ,  Dimin Niu ,  Peng Gu

IPC: G06F13/16 ,  G06F7/544 ,  G06F9/30

Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.

公开(公告)号：US10592121B2

公开(公告)日：2020-03-17

申请号：US15821688

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F15/78 ,  G06F13/42

Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit includes a first interface coupled to a host device and a second interface coupled to the HBM device. The logic circuit receives a first command from the host device through the first interface and converts the received first command to a first processing-in-memory (PIM) command that is sent to the HBM device through the second interface. The first PIM command has a deterministic latency for completion. The logic circuit further receives a second command from the host device through the first interface and converting the received second command to a second PIM command that is sent to the HBM device through the second interface. The second PIM command has a non-deterministic latency for completion.

公开(公告)号：US10379939B2

公开(公告)日：2019-08-13

申请号：US15470657

申请日：2017-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F11/10 ,  G06F21/64 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44

Abstract: A method of performing memory deduplication and single error correction double error detection (SEC-DED) in a computer memory, the method including reading data from an array of memory chips, calculating at least one hash based on the data, checking the one or more hashes against at least one of a physical line ID hash and against a secondary hash, determining whether an error is detected, when an error is detected, correcting the data by changing each bit of the array of the memory chips one at a time until no error is detected, wherein between changing each bit, at least one hash is calculated based on the changed data, and the one or more hash for the new data is compared against one or more of a physical line ID hash and against a secondary hash, and again determining whether an error is detected, and outputting the corrected data when no error is detected.

公开(公告)号：US20190196953A1

公开(公告)日：2019-06-27

申请号：US15913758

申请日：2018-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Peng Gu ,  Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F12/02 ,  G06F17/16 ,  G06F9/30

CPC classification number: G06F12/0207 ,  G06F9/3001 ,  G06F17/16 ,  G06F2212/1024

Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

公开(公告)号：US10073790B2

公开(公告)日：2018-09-11

申请号：US15905348

申请日：2018-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng

IPC: G11C5/00 ,  G11C7/00 ,  G06F12/0897 ,  G06F12/0868 ,  G06F3/06 ,  G06F13/16 ,  G06F12/0811

CPC classification number: G06F12/0897 ,  G06F3/0611 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0884 ,  G06F12/0888 ,  G06F13/1668 ,  G06F2212/6046

Abstract: An electronic system includes: a processor configured to access operation data; a high speed local memory, coupled to the processor, configured to store a limited amount of the operation data; and a memory subsystem, coupled to the high speed local memory, including: a module memory controller configured to access the operational data for the processor and the high speed local memory, a local cache controller, coupled to the module memory controller, including a fast control bus configured to store the operation data, with critical timing in a first tier memory, and a memory tier controller, coupled to the local cache controller, including a reduced performance control bus configured to store the operation data with non-critical timing in a second tier memory.

公开(公告)号：US20180210830A1

公开(公告)日：2018-07-26

申请号：US15481147

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F12/0802

CPC classification number: G06F12/0866 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1041 ,  G06F2212/225 ,  G06F2212/283

Abstract: According to some embodiments of the present invention, there is provided a hybrid cache memory for a processing device having a host processor, the hybrid cache memory comprising: a high bandwidth memory (HBM) configured to store host data; a non-volatile memory (NVM) physically integrated with the HBM in a same package and configured to store a copy of the host data at the HBM; and a cache controller configured to be in bi-directional communication with the host processor, and to manage data transfer between the HBM and NVM and, in response to a command received from the host processor, to manage data transfer between the hybrid cache memory and the host processor.

公开(公告)号：US20180181494A1

公开(公告)日：2018-06-28

申请号：US15905348

申请日：2018-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F12/0897 ,  G06F12/0868 ,  G06F12/0811 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F12/0897 ,  G06F3/0611 ,  G06F12/0811 ,  G06F12/0868 ,  G06F13/1668

Abstract: An electronic system includes: a processor configured to access operation data; a high speed local memory, coupled to the processor, configured to store a limited amount of the operation data; and a memory subsystem, coupled to the high speed local memory, including: a module memory controller configured to access the operational data for the processor and the high speed local memory, a local cache controller, coupled to the module memory controller, including a fast control bus configured to store the operation data, with critical timing in a first tier memory, and a memory tier controller, coupled to the local cache controller, including a reduced performance control bus configured to store the operation data with non-critical timing in a second tier memory.