公开(公告)号：US20130346764A1

公开(公告)日：2013-12-26

申请号：US13532949

申请日：2012-06-26

申请人： Jessica Gullbrand ,  Karthik Sankaranaravanan ,  Willem M. Beltman ,  Eric Baugh ,  Stephen H. Gunther ,  Jay D. Schwartz

发明人： Jessica Gullbrand ,  Karthik Sankaranaravanan ,  Willem M. Beltman ,  Eric Baugh ,  Stephen H. Gunther ,  Jay D. Schwartz

IPC分类号： G06F1/26

CPC分类号： H02M1/44 ,  G06F1/3203 ,  H02M1/36

摘要： In one or more embodiments, a fixed time interval for a system is determined. The fixed time interval corresponds to time between clock ticks. A random time interval is determined based on the fixed time interval and an offset. One or more electronic components affixed to a motherboard are transitioned to a new power state when the random time interval has elapsed. By introducing a randomization to the timing element to a control signal that drives the power state transition, a periodicity for the system is disrupted. The disruption in periodicity mitigates acoustic noise generated by vibrations in electronic components and motherboards affected by current and/or voltage transitions.

摘要翻译： 在一个或多个实施例中，确定系统的固定时间间隔。 固定时间间隔对应于时钟间隔之间的时间。 基于固定时间间隔和偏移确定随机时间间隔。 当随机时间间隔过去时，固定到母板上的一个或多个电子部件转变到新的电源状态。 通过将定时元件的随机化引入到驱动电源状态转换的控制信号，系统的周期性被破坏。 周期性的破坏减轻了受电流和/或电压转换影响的电子元件和母板振动产生的声音噪声。

公开(公告)号：US08611170B2

公开(公告)日：2013-12-17

申请号：US13341868

申请日：2011-12-30

申请人： Timothy Y. Kam ,  Jay D. Schwartz ,  Seongwoo Kim ,  Stephen H. Gunther

发明人： Timothy Y. Kam ,  Jay D. Schwartz ,  Seongwoo Kim ,  Stephen H. Gunther

IPC分类号： G11C5/14

CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

摘要翻译： 使用收集的性能计数器统计信息来生成一组或多个eDRAM有效性预测的嵌入式动态随机存取存储器（eDRAM）的电源管理。 使用一组一个或多个eDRAM有效性阈值，每个eDRAM有效性阈值对应于一组eDRAM有效性预测之一，以确定至少一个eDRAM有效性预测是否超过阈值。 在至少一个eDRAM有效性预测超过其阈值的情况下，将eDRAM转换到新的电源状态。 通过转换到断电状态或自刷新状态并减少eDRAM与上电状态相比所消耗的功率量来实现电源管理。

公开(公告)号：US20130212370A1

公开(公告)日：2013-08-15

申请号：US13842974

申请日：2013-03-15

申请人： Stephen A. Fischer ,  Varghese George ,  Sanjeev Jahagirdar ,  Stephen H. Gunther

发明人： Stephen A. Fischer ,  Varghese George ,  Sanjeev Jahagirdar ,  Stephen H. Gunther

IPC分类号： G06F21/57

CPC分类号： G06F21/57 ,  G06F1/324 ,  G06F1/3296 ,  G06F21/575 ,  G06F21/70 ,  G06F21/81 ,  G06F2221/2101 ,  Y02D10/126

摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.

公开(公告)号：US06308279B1

公开(公告)日：2001-10-23

申请号：US09083281

申请日：1998-05-22

申请人： Bret L. Toll ,  Alan B. Kyker ,  Stephen H. Gunther

发明人： Bret L. Toll ,  Alan B. Kyker ,  Stephen H. Gunther

IPC分类号： G06F126

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/329 ,  Y02D10/128 ,  Y02D10/24 ,  Y02D50/20

摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.

摘要翻译： 一种用于多线程处理器中功率模式转换的方法和装置。 发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。 发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。 指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。 当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。