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    ENHANCING POWER-PERFORMANCE EFFICIENCY IN A COMPUTER SYSTEM
    1.
    发明申请
    ENHANCING POWER-PERFORMANCE EFFICIENCY IN A COMPUTER SYSTEM 有权
    在计算机系统中提高功率性能

    公开(公告)号：US20150370304A1

    公开(公告)日：2015-12-24

    申请号：US14313597

    申请日：2014-06-24

    申请人： HISHAM ABU SALAH ,  ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  PAUL S. DIEFENBAUGH ,  JAY D. SCHWARTZ ,  SHARAD C. TRIPATHI

    发明人： HISHAM ABU SALAH ,  ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  PAUL S. DIEFENBAUGH ,  JAY D. SCHWARTZ ,  SHARAD C. TRIPATHI

    IPC分类号： G06F1/32

    CPC分类号： G06F1/324 ,  G06F1/3206 ,  G06F1/3293 ,  Y02D10/126

    摘要： Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

    摘要翻译： 上述技术可以提高处理器，SoC或计算系统的功率性能效率。 这里描述的实施例响应于在低处理器利用周期内检测到高活动突发的发生，允许将时钟信号的频率增加到峰值频率值。 功率管理单元可以在低或空闲处理器利用周期期间累积预算，并且可以确定高活动信号的突发的活动级别。 如果高活动突发级别超过第一阈值并且累积预算值超过第二阈值，则PMU可以增加提供给处理核心的时钟信号的频率。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING BALANCING POWER AMONG MULTI-FREQUENCY DOMAINS OF A PROCESSOR BASED ON EFFICIENCY RATING SCHEME
    4.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING BALANCING POWER AMONG MULTI-FREQUENCY DOMAINS OF A PROCESSOR BASED ON EFFICIENCY RATING SCHEME 有权
    基于效率评估方案的处理器多频域的能源效率和能源保护的方法，装置和系统，包括平衡功率

    公开(公告)号：US20120173895A1

    公开(公告)日：2012-07-05

    申请号：US13311467

    申请日：2011-12-05

    申请人： Seongwoo Kim ,  Jeremy Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther ,  Travis C. Furrer

    发明人： Seongwoo Kim ,  Jeremy Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther ,  Travis C. Furrer

    IPC分类号： G06F1/00

    CPC分类号： G06F1/329 ,  G06F1/3206 ,  G06F11/3466 ,  Y02D10/24

    摘要： The efficiency rating (ER) of each domain, in a processor, may be compared and then the power budget may be allocated, effectively, among the domains based on the ERs of the domains. The ER may indicate relative advantage among domains in terms of performance return for a given power budget, i.e., a higher effectiveness may be expected in power utilization if the ER is higher for a domain. The ER of a domain may be defined as (scalability factor/cost factor*alpha). The scalability factor may be defined as a performance increase (in %) brought about by an increase in the clock frequency (in %) provided to the domain. The cost factor may be defined as a power budget value required in bringing about an increase in the clock frequency provided to the domain and alpha is an adjustment factor.

    摘要翻译： 可以比较处理器中每个域的效率等级（ER），然后基于域的ER来在域中有效地分配功率预算。 对于给定的功率预算，ER可以指示域之间的性能回报方面的相对优势，即如果ER对于域更高，则在功率利用中可以预期更高的有效性。 域的ER可以定义为（可扩展性因子/成本因子*α）。 可扩展性因素可以被定义为由提供给域的时钟频率（以％计）的增加而导致的性能增加（以％计）。 成本因素可以被定义为使得提供给域的时钟频率增加所需的功率预算值，而α是调整因子。

    Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme
    5.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme 有权
    包括基于效率评估方案的处理器的多频域之间的平衡功率的能量效率和节能的方法，装置和系统

    公开(公告)号：US09239611B2

    公开(公告)日：2016-01-19

    申请号：US13311467

    申请日：2011-12-05

    申请人： Seongwoo Kim ,  Jeremy Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther ,  Travis C. Furrer

    发明人： Seongwoo Kim ,  Jeremy Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther ,  Travis C. Furrer

    IPC分类号： G06F11/34 ,  G06F1/32

    CPC分类号： G06F1/329 ,  G06F1/3206 ,  G06F11/3466 ,  Y02D10/24

    摘要： The efficiency rating (ER) of each domain, in a processor, may be compared and then the power budget may be allocated, effectively, among the domains based on the ERs of the domains. The ER may indicate relative advantage among domains in terms of performance return for a given power budget, i.e., a higher effectiveness may be expected in power utilization if the ER is higher for a domain. The ER of a domain may be defined as (scalability factor/cost factor*alpha). The scalability factor may be defined as a performance increase (in %) brought about by an increase in the clock frequency (in %) provided to the domain. The cost factor may be defined as a power budget value required in bringing about an increase in the clock frequency provided to the domain and alpha is an adjustment factor.

    摘要翻译： 可以比较处理器中每个域的效率等级（ER），然后基于域的ER来在域中有效地分配功率预算。 对于给定的功率预算，ER可以指示域之间的性能回报方面的相对优势，即如果ER对于域更高，则在功率利用中可以预期更高的有效性。 域的ER可以定义为（可扩展性因子/成本因子*α）。 可扩展性因素可以被定义为由提供给域的时钟频率（以％计）的增加而导致的性能增加（以％计）。 成本因素可以被定义为使得提供给域的时钟频率增加所需的功率预算值，而α是调整因子。

    Dynamic Balancing Of Power Across A Plurality Of Processor Domains According To Power Policy Control Bias
    7.
    发明申请
    Dynamic Balancing Of Power Across A Plurality Of Processor Domains According To Power Policy Control Bias 有权
    根据电力政策控制偏差，跨多个处理器域的动态平衡功率

    公开(公告)号：US20140181545A1

    公开(公告)日：2014-06-26

    申请号：US13724798

    申请日：2012-12-21

    申请人： Jeremy J. Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther

    发明人： Jeremy J. Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3206 ,  G06F1/324 ,  Y02D10/126

    摘要： In an embodiment, a processor includes multiple domains including a core domain having at least one core to execute instructions and a graphics domain including at least one graphics engine to perform graphics operations and a power controller to control power consumption of the processor. The power controller may include a logic to receive an indication of a priority domain of the domains and to dynamically allocate power to the domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括多个域，包括具有至少一个核的执行指令的核心域和包括至少一个图形引擎以执行图形操作的图形域，以及功率控制器来控制处理器的功耗。 功率控制器可以包括用于接收域的优先级域的指示并且基于功率限制，一个或多个最大域频率请求和优先级域指示来动态地向域分配功率的逻辑。 描述和要求保护其他实施例。

    Acoustic Noise Mitigation Using Periodicity Disruption
    8.
    发明申请
    Acoustic Noise Mitigation Using Periodicity Disruption 有权
    使用周期性破坏的声学噪声减轻

    公开(公告)号：US20130346764A1

    公开(公告)日：2013-12-26

    申请号：US13532949

    申请日：2012-06-26

    申请人： Jessica Gullbrand ,  Karthik Sankaranaravanan ,  Willem M. Beltman ,  Eric Baugh ,  Stephen H. Gunther ,  Jay D. Schwartz

    发明人： Jessica Gullbrand ,  Karthik Sankaranaravanan ,  Willem M. Beltman ,  Eric Baugh ,  Stephen H. Gunther ,  Jay D. Schwartz

    IPC分类号： G06F1/26

    CPC分类号： H02M1/44 ,  G06F1/3203 ,  H02M1/36

    摘要： In one or more embodiments, a fixed time interval for a system is determined. The fixed time interval corresponds to time between clock ticks. A random time interval is determined based on the fixed time interval and an offset. One or more electronic components affixed to a motherboard are transitioned to a new power state when the random time interval has elapsed. By introducing a randomization to the timing element to a control signal that drives the power state transition, a periodicity for the system is disrupted. The disruption in periodicity mitigates acoustic noise generated by vibrations in electronic components and motherboards affected by current and/or voltage transitions.

    摘要翻译： 在一个或多个实施例中，确定系统的固定时间间隔。 固定时间间隔对应于时钟间隔之间的时间。 基于固定时间间隔和偏移确定随机时间间隔。 当随机时间间隔过去时，固定到母板上的一个或多个电子部件转变到新的电源状态。 通过将定时元件的随机化引入到驱动电源状态转换的控制信号，系统的周期性被破坏。 周期性的破坏减轻了受电流和/或电压转换影响的电子元件和母板振动产生的声音噪声。

    Mechanisms for utilizing efficiency metrics to control embedded dynamic random access memory power states on a semiconductor integrated circuit package
    9.
    发明授权
    Mechanisms for utilizing efficiency metrics to control embedded dynamic random access memory power states on a semiconductor integrated circuit package 有权
    利用效率度量来控制半导体集成电路封装上的嵌入式动态随机存取存储器功率状态的机制

    公开(公告)号：US08611170B2

    公开(公告)日：2013-12-17

    申请号：US13341868

    申请日：2011-12-30

    申请人： Timothy Y. Kam ,  Jay D. Schwartz ,  Seongwoo Kim ,  Stephen H. Gunther

    发明人： Timothy Y. Kam ,  Jay D. Schwartz ,  Seongwoo Kim ,  Stephen H. Gunther

    IPC分类号： G11C5/14

    CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

    摘要翻译： 使用收集的性能计数器统计信息来生成一组或多个eDRAM有效性预测的嵌入式动态随机存取存储器（eDRAM）的电源管理。 使用一组一个或多个eDRAM有效性阈值，每个eDRAM有效性阈值对应于一组eDRAM有效性预测之一，以确定至少一个eDRAM有效性预测是否超过阈值。 在至少一个eDRAM有效性预测超过其阈值的情况下，将eDRAM转换到新的电源状态。 通过转换到断电状态或自刷新状态并减少eDRAM与上电状态相比所消耗的功率量来实现电源管理。