公开(公告)号：US20070252197A1

公开(公告)日：2007-11-01

申请号：US11413248

申请日：2006-04-29

申请人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

发明人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L29/7813 ,  H01L22/12 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

摘要翻译： 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。

公开(公告)号：US20060249791A1

公开(公告)日：2006-11-09

申请号：US11122848

申请日：2005-05-05

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L23/62

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L27/11206

摘要： This invention discloses a one-time programmable (OTP) memory cell. The OTP memory cell includes a dielectric layer disposed between two conductive polysilicon segments wherein the dielectric layer is ready to change from a non-conductive state to a conductive state through an induced voltage breakdown. In a preferred embodiment, one of the conductive polysilicon segments further includes an etch undercut configuration for conveniently inducing the voltage breakdown in the dielectric layer. In a preferred embodiment, the dielectric layer is further formed as sidewalls covering the edges and corners of a first polysilicon segments to conveniently induce a voltage breakdown in the dielectric layer by the edge and corner electrical field effects.

摘要翻译： 本发明公开了一种可编程（OTP）存储单元。 OTP存储单元包括设置在两个导电多晶硅段之间的电介质层，其中介电层准备好通过感应电压击穿从非导电状态改变到导通状态。 在优选实施例中，导电多晶硅段中的一个还包括蚀刻底切配置，用于方便地引起电介质层中的电压击穿。 在优选实施例中，电介质层还被形成为覆盖第一多晶硅段的边缘和角部的侧壁，以便通过边缘和拐角电场效应方便地引起电介质层中的电压击穿。

公开(公告)号：US20060108635A1

公开(公告)日：2006-05-25

申请号：US10996561

申请日：2004-11-23

申请人： Anup Bhalla ,  Sik Lui ,  Sung-Shan Tai

发明人： Anup Bhalla ,  Sik Lui ,  Sung-Shan Tai

IPC分类号： H01L31/113

CPC分类号： H01L29/7813 ,  H01L24/33 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming part of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.

摘要翻译： 本发明公开了一种通过在半导体衬底的（110）晶体取向上形成沟槽的一部分而制造的具有沟槽栅极的改进的MOSFET器件。 沟槽沿着沿着半导体衬底的不同晶体取向形成的沟槽的侧壁和底表面或沟槽的终端覆盖电介质氧化物层。 实施诸如氧化物退火工艺，特殊掩模或SOG工艺的特殊制造工艺以克服非均匀介电层生长的限制。

公开(公告)号：US06509233B2

公开(公告)日：2003-01-21

申请号：US10094476

申请日：2002-03-07

申请人： Mike Chang ,  Sik Lui ,  Sung-Shan Tai

发明人： Mike Chang ,  Sik Lui ,  Sung-Shan Tai

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L21/28167 ,  H01L21/31155 ,  H01L29/42368 ,  H01L29/517

摘要： Cesium is implanted into the gate oxide layer of a vertical trench-gated MOSFET. The cesium, which is an electropositive material, reduces the threshold voltage of the device and lowers the on-resistance by improving the accumulation region adjacent the bottom of the trench.