公开(公告)号：US20220336632A1

公开(公告)日：2022-10-20

申请号：US17858544

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

Abstract: A device includes a substrate, channel layers over the substrate, a gate dielectric layer around the channel layers, a first work function metal layer around the gate dielectric layer, a second work function metal layer over the first work function metal layer, and a passivation layer between the first work function metal layer and the second work function metal layer. The passivation layer merges in space vertically between adjacent ones of the channel layers.

公开(公告)号：US11469326B2

公开(公告)日：2022-10-11

申请号：US17025903

申请日：2020-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Cheng Chen ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien-Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

Abstract: Embodiments of the present disclosure relate to an un-doped or low-doped epitaxial layer formed below the source/drain features. The un-doped or low-doped epitaxial layer protects the source/drain features from damage during replacement gate processes, and also prevent leakage currents in the mesa device. A semiconductor device is disclosed. The semiconductor device includes an epitaxial feature having a dopant of a first concentration, and a source/drain feature in contact with the epitaxial feature. The source/drain feature comprises the dopant of a second concentration, and the second concentration is higher than the first concentration.

公开(公告)号：US11450665B2

公开(公告)日：2022-09-20

申请号：US17082329

申请日：2020-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.

公开(公告)号：US20220246614A1

公开(公告)日：2022-08-04

申请号：US17728247

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

公开(公告)号：US20220238725A1

公开(公告)日：2022-07-28

申请号：US17717477

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/02

Abstract: A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature. A sidewall surface of the dielectric layer facing the gate structure has a convex shape in a top view, and the convex shape has a center portion extending towards the gate structure.

公开(公告)号：US20220238384A1

公开(公告)日：2022-07-28

申请号：US17717429

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Lan ,  Kuan-Ting Pan ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/306 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/321 ,  H01L21/762

Abstract: According to one example, a semiconductor device includes a first region comprising a plurality of nanosheets vertically stacked above a substrate, a second region comprising a fin protruding from the substrate, a first gate structure wrapping around each of the nanosheets, and a second gate structure disposed over the top surface and sidewalls of the fin. A top surface of a topmost nanosheet of the plurality of nanosheets is vertically offset from a top surface of the fin.

公开(公告)号：US20220230922A1

公开(公告)日：2022-07-21

申请号：US17226599

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Jung-Chien Cheng ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.

公开(公告)号：US11387347B2

公开(公告)日：2022-07-12

申请号：US16746547

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Shi Ning Ju

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/8239 ,  H01L29/417 ,  H01L21/02

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

公开(公告)号：US11387181B2

公开(公告)日：2022-07-12

申请号：US17093303

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L23/50 ,  H01L29/78 ,  H01L27/088

Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.

公开(公告)号：US11362001B2

公开(公告)日：2022-06-14

申请号：US16911665

申请日：2020-06-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiao-Han Liu ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Kuan-Lun Cheng

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure formed over a substrate. The semiconductor structure further includes first nanostructures, second nanostructures, third nanostructures, and fourth nanostructures. The semiconductor structure further includes a first gate structure wrapping around the first nanostructures and the second nanostructures, and a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a first lateral distance between the first fin structure and the second fin structure is shorter than a second lateral distance between the third fin structure and the fourth fin structure, and the first fin structure and the second fin structure are narrower than the third fin structure and the fourth fin structure.