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    MULTI-CHANNEL DEVICES AND METHODS OF MANUFACTURE
    82.
    发明申请
    MULTI-CHANNEL DEVICES AND METHODS OF MANUFACTURE 有权

    公开(公告)号：US20210375683A1

    公开(公告)日：2021-12-02

    申请号：US16888239

    申请日：2020-05-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L27/088 ,  H01L21/3065

    Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

    Dummy Fin with Reduced Height and Method Forming Same
    84.
    发明申请
    Dummy Fin with Reduced Height and Method Forming Same 有权

    公开(公告)号：US20210327763A1

    公开(公告)日：2021-10-21

    申请号：US16942076

    申请日：2020-07-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Te-Yung Liu ,  Chih-Han Lin

    IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088

    Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.

    Structure and formation method of semiconductor device with gate stacks
    85.
    发明授权
    Structure and formation method of semiconductor device with gate stacks 有权

    公开(公告)号：US11121130B2

    公开(公告)日：2021-09-14

    申请号：US16730576

    申请日：2019-12-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

    IPC: H01L27/088 ,  H01L23/31 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

    Abstract: Structures and formation methods of a semiconductor device are provided. The method includes forming a first fin structure and a second fin structure over a substrate, and forming first, second and third dummy gate stacks over the substrate. The first dummy gate stack and the second dummy gate stack partially cover the first fin structure and the second fin structure respectively. The third dummy gate stack is between the first dummy gate stack and the second dummy gate stack. The method also includes partially removing the third dummy gate stack such that a semiconductor layer of the third dummy gate stack remains over the substrate, forming a protection layer over the semiconductor layer, and replacing the first dummy gate stack and second dummy gate stack with a first gate stack and a second gate stack, respectively.

    Semiconductor Devices and Methods of Formation
    86.
    发明申请
    Semiconductor Devices and Methods of Formation 有权

    公开(公告)号：US20210273072A1

    公开(公告)日：2021-09-02

    申请号：US16889427

    申请日：2020-06-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

    Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.

    Gate Formation Process
    87.
    发明申请
    Gate Formation Process 有权

    公开(公告)号：US20210265219A1

    公开(公告)日：2021-08-26

    申请号：US16800871

    申请日：2020-02-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

    IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/308

    Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

    Method of forming FinFET devices with embedded air gaps
    88.
    发明授权
    Method of forming FinFET devices with embedded air gaps 有权

    公开(公告)号：US11043408B2

    公开(公告)日：2021-06-22

    申请号：US16203987

    申请日：2018-11-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Cheng Chang ,  Chih-Han Lin

    IPC: H01L21/764 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06

    Abstract: A dummy gate layer is formed over a substrate. A patterned mask is formed over the dummy gate layer. The patterned mask includes an opening. The opening is etched into the dummy gate layer. The patterned mask serves as a protective mask as the opening is etched. A lateral etching process is performed to portions of the dummy gate layer laterally exposed by the opening. The lateral etching process etches away the dummy gate layer without substantially affecting the patterned mask. After the lateral etching process is performed, a dielectric material is formed in the opening. An air gap is formed in the dielectric material. After the air gap is formed, the patterned mask and portions of the dielectric material formed over the patterned mask are removed. The dummy gate layer is replaced with a metal-containing gate.

    Fin Structure and Method of Forming Same Through Two-Step Etching Processes
    90.
    发明申请
    Fin Structure and Method of Forming Same Through Two-Step Etching Processes 有权

    公开(公告)号：US20210066290A1

    公开(公告)日：2021-03-04

    申请号：US17097423

    申请日：2020-11-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

    IPC: H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L21/8234

    Abstract: A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.

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