公开(公告)号：US20200212188A1

公开(公告)日：2020-07-02

申请号：US16812311

申请日：2020-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Alexei Sadovnikov ,  Eugene C Davis

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/221 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/40

Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure located between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon oxide.

公开(公告)号：US20190252410A1

公开(公告)日：2019-08-15

申请号：US16395116

申请日：2019-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Jeffrey A. Babcock

IPC: H01L27/12 ,  H01L27/082 ,  H01L29/06 ,  H01L29/08 ,  H01L29/735 ,  H01L29/66 ,  H01L29/10 ,  H01L23/535 ,  H01L29/732

CPC classification number: H01L27/1203 ,  H01L23/535 ,  H01L27/082 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/10 ,  H01L29/1008 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/735

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

公开(公告)号：US10224402B2

公开(公告)日：2019-03-05

申请号：US14540105

申请日：2014-11-13

Applicant: Texas Instruments Incorporated

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov

IPC: H01L29/08 ,  H01L27/06 ,  H01L29/66 ,  H01L29/735 ,  H01L29/732 ,  H01L29/06 ,  H01L21/8249

Abstract: In a lateral BJT formed using a BiCMOS process, the collector-to-emitter breakdown voltage (BVCEO) and BJT's gain, are improved by forming a graded collector contact region with lower doping levels toward the base contact.

公开(公告)号：US10163680B1

公开(公告)日：2018-12-25

申请号：US15709039

申请日：2017-09-19

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Scott Kelly Montgomery

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/74 ,  H01L29/10

Abstract: A method of forming an IC includes forming a buried layer (BL) doped a second type in a substrate doped a first type. Deep trenches are etched including narrower inner trench rings and wider outer trench rings through to the BL. A first deep sinker implanting uses ions of the second type with a first dose, a first energy, and a first tilt angle. A second deep sinker implant uses ions of the second type with a second dose that than the first energy, and a second tilt angle

公开(公告)号：US10153269B2

公开(公告)日：2018-12-11

申请号：US15679592

申请日：2017-08-17

Applicant: Texas Instruments Incorporated

Inventor： Andrew D. Strachan ,  Alexei Sadovnikov ,  Gang Xue ,  Dening Wang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66

Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm−3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

公开(公告)号：US20180053765A1

公开(公告)日：2018-02-22

申请号：US15681466

申请日：2017-08-21

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Binghua Hu ,  Alexei Sadovnikov ,  Guru Mathur

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

公开(公告)号：US20170200712A1

公开(公告)日：2017-07-13

申请号：US14991881

申请日：2016-01-08

Applicant: Texas Instruments Incorporated

Inventor： Andrew D. Strachan ,  Alexei Sadovnikov ,  Gang Xue ,  Dening Wang

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/6609 ,  H01L29/66113 ,  H01L29/861 ,  H01L29/8618

Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm−3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

公开(公告)号：US09640611B2

公开(公告)日：2017-05-02

申请号：US14219760

申请日：2014-03-19

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Jeffrey A. Babcock

IPC: H01L29/732 ,  H01L27/082 ,  H01L29/00 ,  H01L29/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L27/1203 ,  H01L23/535 ,  H01L27/082 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/10 ,  H01L29/1008 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/735

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

公开(公告)号：US20160163598A1

公开(公告)日：2016-06-09

申请号：US14561008

申请日：2014-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov ,  Andrew D. Strachan

IPC: H01L21/8249 ,  H01L29/40 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/866

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

Abstract translation: BiCMOS半导体结构中的双极型晶体管的beta通过用两种注入形成双极型晶体管的发射极来增加：在形成源极和漏极区域的同时形成第一发射极区域的源极 - 漏极注入，以及 在形成另一区域的同时形成第二发射极区域的附加注入。 附加植入物具有大于源极 - 漏极植入物的植入能量的植入能量。