公开(公告)号：US20130341705A1

公开(公告)日：2013-12-26

申请号：US14015029

申请日：2013-08-30

Applicant: Texas Instruments Incorporated

Inventor： Venkat Raghavan ,  Andrew D. Strachan

IPC: H01L27/06 ,  H01L29/66

CPC classification number: H01L27/06 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/782

Abstract: In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes.

Abstract translation: 在LDMOS器件中，通过用肖特基二极管代替一个或多个n +源极区，将肖特基二极管集成到LDMOS中来调节泄漏和正向传导参数。

公开(公告)号：US09595480B2

公开(公告)日：2017-03-14

申请号：US14561008

申请日：2014-12-04

Applicant: Texas Instruments Incorporated

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov ,  Andrew D. Strachan

IPC: H01L21/337 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L27/06 ,  H01L21/8238

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/866

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

Abstract translation: BiCMOS半导体结构中的双极型晶体管的beta通过用两种注入形成双极型晶体管的发射极来增加：在形成源极和漏极区域的同时形成第一发射极区域的源极 - 漏极注入，以及 在形成另一区域的同时形成第二发射极区域的附加注入。 附加植入物具有大于源极 - 漏极植入物的植入能量的植入能量。

公开(公告)号：US09831135B2

公开(公告)日：2017-11-28

申请号：US15420296

申请日：2017-01-31

Applicant: Texas Instruments Incorporated

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov ,  Andrew D. Strachan

IPC: H01L21/337 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08 ,  H01L27/06 ,  H01L29/866 ,  H01L29/06 ,  H01L29/732

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/866

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

公开(公告)号：US20170140991A1

公开(公告)日：2017-05-18

申请号：US15420296

申请日：2017-01-31

Applicant: Texas Instruments Incorporated

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov ,  Andrew D. Strachan

IPC: H01L21/8249 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/866

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

公开(公告)号：US08686502B2

公开(公告)日：2014-04-01

申请号：US14015029

申请日：2013-08-30

Applicant: Texas Instruments Incorporated

Inventor： Venkat Raghavan ,  Andrew D. Strachan

IPC: H01L27/06

CPC classification number: H01L27/06 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/782

Abstract: In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes.

Abstract translation: 在LDMOS器件中，通过用肖特基二极管代替一个或多个n +源极区，将肖特基二极管集成到LDMOS中来调节泄漏和正向传导参数。

公开(公告)号：US11552183B2

公开(公告)日：2023-01-10

申请号：US16897382

申请日：2020-06-10

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Andrew D. Strachan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L21/266 ,  H01L29/40

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

公开(公告)号：US10153269B2

公开(公告)日：2018-12-11

申请号：US15679592

申请日：2017-08-17

Applicant: Texas Instruments Incorporated

Inventor： Andrew D. Strachan ,  Alexei Sadovnikov ,  Gang Xue ,  Dening Wang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66

Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm−3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

公开(公告)号：US20170200712A1

公开(公告)日：2017-07-13

申请号：US14991881

申请日：2016-01-08

Applicant: Texas Instruments Incorporated

Inventor： Andrew D. Strachan ,  Alexei Sadovnikov ,  Gang Xue ,  Dening Wang

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/6609 ,  H01L29/66113 ,  H01L29/861 ,  H01L29/8618

Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm−3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

公开(公告)号：US20160163598A1

公开(公告)日：2016-06-09

申请号：US14561008

申请日：2014-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov ,  Andrew D. Strachan

IPC: H01L21/8249 ,  H01L29/40 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/866

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

Abstract translation: BiCMOS半导体结构中的双极型晶体管的beta通过用两种注入形成双极型晶体管的发射极来增加：在形成源极和漏极区域的同时形成第一发射极区域的源极 - 漏极注入，以及 在形成另一区域的同时形成第二发射极区域的附加注入。 附加植入物具有大于源极 - 漏极植入物的植入能量的植入能量。

公开(公告)号：US10714594B2

公开(公告)日：2020-07-14

申请号：US15813934

申请日：2017-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Andrew D. Strachan

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/40

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.