公开(公告)号：US6165913A

公开(公告)日：2000-12-26

申请号：US957922

申请日：1997-10-27

Applicant: Tony Lin ,  Heng-Sheng Huang

Inventor： Tony Lin ,  Heng-Sheng Huang

IPC: H01L21/336 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/308

CPC classification number: H01L29/6659 ,  H01L29/4983 ,  H01L29/6656

Abstract: A method for manufacturing spacers comprising the steps of first providing a semiconductor substrate having a gate electrode already formed thereon, and then sequentially depositing oxide, silicon nitride and oxide over the gate electrode and the substrate to form a first oxide layer, a silicon nitride layer and a second oxide layer. Subsequently, the second oxide layer is etched to form an oxide spacer above the silicon nitride layer. Thereafter, using the oxide spacer as a mask, a dry etching method having a high etching selectivity ratio for silicon nitride/oxide is used to etch the silicon nitride layer to form a silicon nitride spacer. Finally, the oxide spacer is removed using an oxide dip method. The silicon nitride spacers of this invention can have a greater thickness, more thickness uniformity, and a higher reliability for hot carriers. In addition, the method used in the invention can have a better control over the thickness.

Abstract translation: 一种用于制造间隔物的方法，包括以下步骤：首先提供其上已经形成有栅电极的半导体衬底，然后在栅电极和衬底上依次沉积氧化物，氮化硅和氧化物以形成第一氧化物层，氮化硅层 和第二氧化物层。 随后，蚀刻第二氧化物层以在氮化硅层上形成氧化物间隔物。 此后，使用氧化物间隔物作为掩模，使用对于氮化硅/氧化物具有高蚀刻选择性比的干蚀刻方法来蚀刻氮化硅层以形成氮化硅间隔物。 最后，使用氧化物浸渍法除去氧化物间隔物。 本发明的氮化硅间隔物可以具有更大的厚度，更多的厚度均匀性和对热载体的更高的可靠性。 此外，本发明中使用的方法可以更好地控制厚度。

公开(公告)号：US6153478A

公开(公告)日：2000-11-28

申请号：US14755

申请日：1998-01-28

Applicant: Tony Lin ,  Wen-Kuan Yeh ,  Heng-Sheng Huang

Inventor： Tony Lin ,  Wen-Kuan Yeh ,  Heng-Sheng Huang

IPC: H01L21/762 ,  H01L21/00

CPC classification number: H01L21/76235

Abstract: The process includes the following steps. At first, a masking layer is formed over the semiconductor substrate. A portion of the masking layer is then removed to form an opening to the semiconductor substrate. Sidewall spacers are formed on the opening and a portion of the semiconductor substrate is removed to form a trench, through an aperture defined by the sidewall spacers. The sidewall spacers is then removed and a liner layer is formed conformably over the trench.

Abstract translation: 该过程包括以下步骤。 首先，在半导体衬底上形成掩模层。 然后去除掩模层的一部分以形成到半导体衬底的开口。 侧壁间隔件形成在开口上，并且半导体衬底的一部分被去除以形成通过由侧壁间隔件限定的孔的沟槽。 然后去除侧壁间隔物，并且衬垫层顺应地形成在沟槽上。

公开(公告)号：US6083783A

公开(公告)日：2000-07-04

申请号：US94053

申请日：1998-06-09

Applicant: Tony Lin ,  Wen-Kuan Yeh ,  Jenn Tsao

Inventor： Tony Lin ,  Wen-Kuan Yeh ,  Jenn Tsao

IPC: H01L21/8238

CPC classification number: H01L21/823807

Abstract: A method of manufacturing a complementary metal-oxide-semiconductor that utilizes a slight change in the patterned photoresist layer for forming the lightly doped drain structure of an NMOS and the halo implantation region during CMOS fabrication. By forming a photoresist layer that exposes the p-well region where a well pickup structure is to be formed, the distance between the photoresist layer and the gate is increased, thereby eliminating the restrictions imposed upon the tilt angle in a halo implantation. Later, the lightly doped n-type impurities in the well pickup region can be compensated for by the p-type impurity implantation when the PMOS source/drain regions are formed. Hence, the lightly doped n-type well pickup region can be reverted to a p-type impurity doped region.

Abstract translation: 制造互补金属氧化物半导体的方法，其利用图案化的光致抗蚀剂层中的轻微变化，以在CMOS制造期间形成NMOS的轻掺杂漏极结构和卤注入区。 通过形成露出要形成阱拾取结构的p阱区的光致抗蚀剂层，光致抗蚀剂层和栅极之间的距离增加，从而消除了在光晕注入中施加在倾斜角上的限制。 然后，当形成PMOS源极/漏极区域时，可以通过p型杂质注入来补偿阱拾取区域中的轻掺杂n型杂质。 因此，轻掺杂的n型阱拾取区域可以被还原成p型杂质掺杂区域。

公开(公告)号：US06064107A

公开(公告)日：2000-05-16

申请号：US56276

申请日：1998-04-07

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/00

CPC classification number: H01L29/66583 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/665

Abstract: A semiconductor device comprises a semiconductor substrate, a source/drain region formed in the substrate, a gate oxide layer on the substrate between the source/drain region, a conductive layer on the gate oxide layer, a spacer around a side wall of the gate, and an air gap between the gate and the spacer. The spacer is not directly connected with the gate. The air gap is formed between the gate and the spacer.

Abstract translation: 半导体器件包括半导体衬底，形成在衬底中的源极/漏极区，源极/漏极区之间的衬底上的栅极氧化物层，栅极氧化物层上的导电层，栅极侧壁周围的间隔物 ，以及栅极和间隔物之间​​的气隙。 间隔件不直接与门连接。 气隙形成在栅极和间隔物之间​​。

公开(公告)号：US6063660A

公开(公告)日：2000-05-16

申请号：US52685

申请日：1998-03-31

Applicant: Hua-Chou Tseng ,  Tony Lin ,  Horng-Nan Chern

Inventor： Hua-Chou Tseng ,  Tony Lin ,  Horng-Nan Chern

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A fabricating method and a structure of a stacked-type capacitor is provided comprising forming a first dielectric layer having a first via on a semiconductor substrate. A first conductive layer is filled into the first via. Then, insulating layers and dielectric layers are formed. A photolithography step is used to form a second dendriform via in the insulating layers and the dielectric layers. A second conductive layer is filled in the second dendriform via. The insulating layers and conductive layers are removed to form a dendriform lower electrode. The dendriform electrode provides a larger surface area to increase capacitance. Further, a polysilicon layer of hemispherical grains is formed to increase the surface area of the lower electrode.

Abstract translation: 提供叠层型电容器的制造方法和结构，包括在半导体衬底上形成具有第一通孔的第一介电层。 第一导电层被填充到第一通孔中。 然后，形成绝缘层和电介质层。 使用光刻步骤在绝缘层和电介质层中形成第二树状通道。 第二导电层填充在第二树状通孔中。 去除绝缘层和导电层以形成树状下电极。 树状电极提供更大的表面积以增加电容。 此外，形成半球状晶粒的多晶硅层以增加下电极的表面积。

公开(公告)号：US6015753A

公开(公告)日：2000-01-18

申请号：US103888

申请日：1998-06-24

Applicant: Tony Lin ,  Hua-Chou Tseng ,  Water Lur

Inventor： Tony Lin ,  Hua-Chou Tseng ,  Water Lur

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01R13/10

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41783

Abstract: A method of forming a self-aligned salicide is provided. The invention twice performs selective epitaxial growth to form an amorphous silicon layer on gate electrodes and source/drain regions of a substrate after forming the gate electrodes and the source/drain regions. Then, a molybdenum impurity is doped to perform a silicidation process and to convert a metal deposited on the substrate into a salicide layer.

Abstract translation: 提供了形成自对准硅化物的方法。 本发明在形成栅极电极和源极/漏极区域之后，两次执行选择性外延生长以在衬底的栅极电极和源极/漏极区域上形成非晶硅层。 然后，掺杂钼杂质以进行硅化工艺并将沉积在衬底上的金属转化成自对准硅化物层。

公开(公告)号：US6013569A

公开(公告)日：2000-01-11

申请号：US888752

申请日：1997-07-07

Applicant: Water Lur ,  Tony Lin

Inventor： Water Lur ,  Tony Lin

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/335 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L29/6659 ,  H01L21/28247 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66545

Abstract: Silicidation of a polysilicon line having frcc upper sidewalls is performed so that no stress is applied to the sidewalls of the polysilicon line, resulting in the formation of a reduced stress silicide structure. This is accomplished by forming a polysilicon line having spacers on either side which extend above the upper surface of the polysilicon line but which are spaced from the edge of the polysilicon line. A layer of a metal such as titanium or tungsten is provided in contact with the top surface polysilicon line. The structure is annealed to cause the metal to react with the polysilicon to form a layer of silicide. Since the upper side portions of the polysilicon line are spaced away from the spacers during the silicidation anneal, the growing silicide region has room to expand without being subjected to lateral stresses in the silicidation process. The suicide is formed in a reduced stress condition, as compared to conventional processes, so that the silicide layer produced will be more readily converted to the desired low resistivity phase of silicide.

Abstract translation: 执行具有frcc上侧壁的多晶硅线的硅化，使得没有应力施加到多晶硅线的侧壁，导致形成应力减小的硅化物结构。 这是通过在多晶硅线的上表面上方延伸但与多晶硅线的边缘间隔开的任一侧上形成具有间隔物的多晶硅线来实现的。 提供与顶表面多晶硅线接触的诸如钛或钨的金属层。 将该结构退火以使金属与多晶硅反应形成一层硅化物。 由于在硅化退火期间多晶硅线的上侧部分与间隔物间隔开，所以生长的硅化物区域具有膨胀的空间，而不会在硅化过程中受到横向应力。 与常规方法相比，自杀在降低的应力条件下形成，使得所生成的硅化物层将更容易地转化为期望的硅化物的低电阻率相。

公开(公告)号：US5990015A

公开(公告)日：1999-11-23

申请号：US41567

申请日：1998-03-12

Applicant: Tony Lin ,  Yimin Huang ,  Tri-Rung Yew

Inventor： Tony Lin ,  Yimin Huang ,  Tri-Rung Yew

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76813 ,  H01L21/76807

Abstract: A dual damascene process can be used to form an interconnect. A first dielectric layer is formed on a semiconductor substrate having a device layer formed thereon. A stop layer is formed on the first dielectric layer and a second dielectric layer is formed on the stop layer. A hard mask layer is formed and patterned on the second dielectric layer so that an opening is formed to expose the second dielectric layer therewithin. The second dielectric layer, the stop layer and a part of the first dielectric layer are etched within the opening by photolithography and etching, so that a contact window is formed. Using the hard mask layer as a hard mask, an etching is performed so that a metal trench penetrating through the second dielectric layer is formed, and the device layer within the contact window is exposed.

Abstract translation: 可以使用双镶嵌工艺来形成互连。 在其上形成有器件层的半导体衬底上形成第一介电层。 在第一电介质层上形成阻挡层，在停止层上形成第二电介质层。 在第二电介质层上形成并图案化硬掩模层，从而形成开口以在其中露出第二介电层。 通过光刻和蚀刻在开口内蚀刻第二介电层，停止层和第一介电层的一部分，从而形成接触窗。 使用硬掩模层作为硬掩模，进行蚀刻，从而形成穿过第二介电层的金属沟槽，并且暴露接触窗内的器件层。

公开(公告)号：US5972763A

公开(公告)日：1999-10-26

申请号：US9335

申请日：1998-01-20

Applicant: Jih-Wen Chou ,  Tony Lin

Inventor： Jih-Wen Chou ,  Tony Lin

IPC: H01L21/336 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66598 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating an air-gap spacer of a metal-oxide-semiconductor device includes the following steps. First, a substrate having a gate oxide layer and a polysilicon layer successively formed is provided. The polysilicon layer and the gate oxide layer are patterned to form a gate electrode region. A silicon nitride layer and an oxide layer are successively formed on the surface of the substrate and the surface of the gate electrode region. The oxide layer and the silicon nitride layer are anisotropically etched to form a cross-sectional L-shaped silicon nitride layer and a first spacer at the sidewall of the gate electrode region. After the first spacer is removed, an ion implantation is performed to form an extended lightly doped region below the L-shaped silicon nitride layer in the substrate and a lightly doped region in the substrate surrounding the extended lightly doped region. A second spacer is formed at the sidewall of the L-shaped silicon nitride layer wherein the second spacer covers the L-shaped silicon nitride layer. An ion implantation process is performed to form source/drain regions, using the second spacer and the gate electrode region as masks. The L-shaped silicon nitride layer is removed to form an L-shaped air-gap region.

Abstract translation: 制造金属氧化物半导体器件的气隙间隔物的方法包括以下步骤。 首先，提供依次形成有栅氧化层和多晶硅层的基板。 图案化多晶硅层和栅极氧化物层以形成栅极电极区域。 在衬底的表面和栅电极区域的表面上依次形成氮化硅层和氧化物层。 各向异性蚀刻氧化物层和氮化硅层，以在栅电极区域的侧壁处形成横截面的L形氮化硅层和第一间隔物。 在去除第一间隔物之后，进行离子注入以在衬底中的L形氮化硅层下方形成延伸的轻掺杂区域，以及在包围扩展的轻掺杂区域的衬底中的轻掺杂区域。 第二间隔件形成在L形氮化硅层的侧壁处，其中第二间隔件覆盖L形氮化硅层。 执行离子注入工艺以形成源极/漏极区域，使用第二间隔物和栅极电极区域作为掩模。 去除L形氮化硅层以形成L形气隙区域。

公开(公告)号：US5895254A

公开(公告)日：1999-04-20

申请号：US993500

申请日：1997-12-18

Applicant: Kuo-Tai Huang ,  Tony Lin ,  Water Lur

Inventor： Kuo-Tai Huang ,  Tony Lin ,  Water Lur

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224 ,  Y10S148/05

Abstract: A method for forming a shallow trench isolation structure comprising the steps of sequentially forming a pad oxide layer and a mask layer over a substrate, then patterning the mask layer and the pad oxide layer. Next, an opening is formed in the mask layer, wherein the sidewall of the opening in the mask layer forms a sharp angle with the substrate layer below. Thereafter, the substrate is etched from the opening down to form a trench. In a subsequent step, insulating material is deposited into the trench forming an insulating layer rising to a level higher than the mask layer, and accompanying by the formation of a protuberance at the side of the insulating layer. Subsequently, the mask layer is removed, and then portions of the pad oxide layer is removed to form a spacer on the upper side of the insulating layer. Finally, the pad oxide layer above the substrate is removed to complete the formation of the shallow trench isolation structure. Due to the presence of a spacer, resistance against subsequent etching is increased at the junction between the trench insulating layer and the substrate layer. Thus, kink effect caused by the over-etching of the insulating layer is prevented.

Abstract translation: 一种用于形成浅沟槽隔离结构的方法，包括以下步骤：在衬底上顺序形成焊盘氧化物层和掩模层，然后对掩模层和焊盘氧化物层进行图案化。 接下来，在掩模层中形成开口，其中掩模层中的开口的侧壁与下面的基底层形成锐角。 此后，从开口向下蚀刻衬底以形成沟槽。 在随后的步骤中，将绝缘材料沉积到沟槽中，形成上升到高于掩模层的水平的绝缘层，并伴随着在绝缘层一侧形成突起。 随后，去除掩模层，然后去除焊盘氧化物层的一部分，以在绝缘层的上侧形成间隔物。 最后，去除衬底上方的衬垫氧化物层以完成浅沟槽隔离结构的形成。 由于存在间隔物，在沟槽绝缘层和衬底层之间的结处增加了对后续蚀刻的抵抗力。 因此，防止了由绝缘层的过度蚀刻引起的扭结效应。