公开(公告)号：US07307911B1

公开(公告)日：2007-12-11

申请号：US11460464

申请日：2006-07-27

申请人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

发明人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： An apparatus for sensing the state of a programmable resistive memory element device includes a latch device is coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg. The latch device is configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg. The fuse and reference resistance legs are further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

摘要翻译： 一种用于感测可编程电阻式存储元件器件的状态的装置包括一个锁存器件耦合到一个熔丝节点和一个参考节点，该熔断器节点包含在一个保险丝支脚内，而该参考节点配置在一个参考电阻支路内。 闩锁装置被配置为检测由于感测电流通过保险丝腿和参考电阻腿而导致在参考节点和熔丝节点之间产生的差分信号。 熔丝和参考电阻支腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流水平。

公开(公告)号：US07093171B2

公开(公告)日：2006-08-15

申请号：US10115348

申请日：2002-04-03

申请人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

发明人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

公开(公告)号：US07061821B2

公开(公告)日：2006-06-13

申请号：US10072346

申请日：2002-02-06

申请人： Paul William Coteus ,  William Paul Hovis ,  William Wu Shen ,  Toshiaki Kirihata

发明人： Paul William Coteus ,  William Paul Hovis ,  William Wu Shen ,  Toshiaki Kirihata

IPC分类号： G11C11/00

CPC分类号： G11C29/50008 ,  A61K8/22 ,  A61Q11/00 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

摘要： The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array.Techniques are advanced involving data responsive selectable array circuitry modification for such operations as address correctness verification, machine timing and component drift correction purposes.The principles are illustrated with memory systems built of Synchronous Dynamic Random Access Memory with Double Data Rate (SDRAM-DDR) elements.

公开(公告)号：US20050144373A1

公开(公告)日：2005-06-30

申请号：US10748333

申请日：2003-12-31

申请人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing Luk

发明人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing Luk

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/1694 ,  Y02D10/14

摘要： A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

摘要翻译： 公开了一种在诸如读取或写入操作的数据操作期间同时激活至少两个不同的存储器阵列的存储器系统。 示例性实施例包括包含多个阵列的存储器系统，每个阵列与公共控制器通信，其中阵列由不同的电源电压（Vdd）激活。 当处理器发送命令以检索或写入数据到存储器系统时，寻址两个或更多个阵列以提供所需的数据。 通过在不同阵列之间适当分割数据，数据读取的效率得到提高。

公开(公告)号：US20050122801A1

公开(公告)日：2005-06-09

申请号：US11031138

申请日：2005-01-07

申请人： Louis Hsu ,  Gregory Fredeman ,  Rajiv Joshi ,  Toshiaki Kirihata

发明人： Louis Hsu ,  Gregory Fredeman ,  Rajiv Joshi ,  Toshiaki Kirihata

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size. Furthermore, a method is provided for replacing faulty wordlines of a memory array including the steps of: selecting a repair field size; storing at least one faulty address into a first memory; and copying the stored at least one faulty address from the first memory into a variable number of storage cells of a second memory, wherein each storage cell of said second memory corresponds to a respective bank of said plurality of banks; and wherein the variable number of storage cells is in accordance with the selected repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。 此外，提供了一种用于替换存储器阵列的错误字线的方法，包括以下步骤：选择修复字段大小; 将至少一个故障地址存储到第一存储器中; 以及将存储的至少一个故障地址从第一存储器复制到第二存储器的可变数量的存储单元中，其中所述第二存储器的每个存储单元对应于所述多个存储体的相应存储体; 并且其中所述可变数量的存储单元符合所选择的修复字段大小。

公开(公告)号：US20050002223A1

公开(公告)日：2005-01-06

申请号：US10688744

申请日：2003-10-17

申请人： Paul Coteus ,  Brian Ji ,  Toshiaki Kirihata ,  Joseph Macri ,  John Ross

发明人： Paul Coteus ,  Brian Ji ,  Toshiaki Kirihata ,  Joseph Macri ,  John Ross

IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C29/02 ,  G11C11/00

CPC分类号： G11C29/50008 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

摘要： A selectable function is provided that permits the impedance of an output driver or an addressable memory device to be configured without adding extra signal connections. The output driver impedance control function of the invention is achieved through the use of the data bus of a memory array for control. The data lines thus serve two purposes one for normal use and the other for control of the impedance. In the invention, the output impedance of each DRAM in a subassembly array that drives a common data bus is individually separately adjusted.

摘要翻译： 提供了一种可选功能，允许在不添加额外信号连接的情况下配置输出驱动器或可寻址存储器件的阻抗。 本发明的输出驱动器阻抗控制功能通过使用用于控制的存储器阵列的数据总线来实现。 因此，数据线用于正常使用的两个目的，另一个用于控制阻抗。 在本发明中，驱动公共数据总线的子组件阵列中的每个DRAM的输出阻抗分别单独调整。

公开(公告)号：US06799290B1

公开(公告)日：2004-09-28

申请号：US09512756

申请日：2000-02-25

申请人： Toshiaki Kirihata ,  Gerhard Mueller ,  David Russell Hanson

发明人： Toshiaki Kirihata ,  Gerhard Mueller ,  David Russell Hanson

IPC分类号： G11C2900

CPC分类号： G11C29/02

摘要： A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, and transferring data into the data path. Components are disabled to isolate at least one stage of the plurality of stages such that data written to or read from the at least one stage is available at an output. The data at the output is preferably compared to expected data. Alternately, system level calibration between devices may be performed to ensure proper communication between devices without destroying data in a memory array and making a dynamic data skew calibration possibly while running an application.

摘要翻译： 根据本发明的用于测试半导体存储器件的数据路径的方法包括提供包括数据路径中的多个级并将数据传送到数据路径的半导体存储器件。 组件被禁用以隔离多个级中的至少一个级，使得写入或从至少一个级读取的数据在输出端可用。 优选地将输出端的数据与预期数据进行比较。 或者，可以执行设备之间的系统级校准，以确保设备之间的正确通信，而不会破坏存储器阵列中的数据并且在运行应用时可能进行动态数据偏移校准。

公开(公告)号：US06680857B2

公开(公告)日：2004-01-20

申请号：US09964208

申请日：2001-09-26

申请人： Gerhard Mueller ,  Toshiaki Kirihata

发明人： Gerhard Mueller ,  Toshiaki Kirihata

IPC分类号： H01L27020

CPC分类号： G11C29/70

摘要： Multiple conductive paths are provided in a circuit portion between a circuit element and a logic block, enabling repairing of defects in the conductive line coupling the circuit element and logic blocks without the use of fusing.

摘要翻译： 在电路元件和逻辑块之间的电路部分提供多个导电路径，能够修复在不使用熔断的情况下连接电路元件和逻辑块的导线中的缺陷。

公开(公告)号：US06674676B1

公开(公告)日：2004-01-06

申请号：US10444226

申请日：2003-05-23

申请人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

发明人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

IPC分类号： G11C700

CPC分类号： G11C29/846 ,  G11C2207/104

摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.

摘要翻译： 一种列冗余系统，包括用于执行各个微单元内的列元素的冗余交换操作的列冗余设备。 列冗余装置还包括熔丝信息存储装置，第一存储体地址解码机构对与读取操作相关的第一微小区对应的读存储体地址进行解码，第二存储体地址解码机构对与 访问用于写操作的第二微小区。 如果存在包含在第一微单元内的至少一个有缺陷的列元素，则列冗余设备生成与第一微单元中的至少一个缺陷列元素对应的内部列地址。 类似地，如果在第二微小区内包含至少一个有缺陷的列元素，则列冗余设备产生对应于第二微小区中的至少一个缺陷列元素的内部列地址。

公开(公告)号：US06522171B2

公开(公告)日：2003-02-18

申请号：US09759011

申请日：2001-01-11

申请人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

发明人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

IPC分类号： H03K19096

CPC分类号： H03K19/0016 ,  H03K19/0963

摘要： A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.