公开(公告)号：US07609577B2

公开(公告)日：2009-10-27

申请号：US11872273

申请日：2007-10-15

申请人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

发明人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构包括用于感测可编程电阻性存储元件装置的状态的装置，该装置还包括耦合到熔丝节点和参考节点的锁存装置，所述熔丝节点包括 所述锁存装置被配置为检测在所述参考节点和所述熔丝节点之间产生的差动信号，这是由于感测电流通过所述保险丝腿和所述参考电阻腿的结果; 并且熔丝和参考电阻腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流电平。

公开(公告)号：US07525831B2

公开(公告)日：2009-04-28

申请号：US11868046

申请日：2007-10-05

申请人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

发明人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

IPC分类号： G11C11/00

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.

摘要翻译： 用于确定可编程电阻性存储元件的状态的方法包括使第一电平电流通过包括可编程电阻存储器元件的测试电路的熔丝支脚和参考电阻支路; 检测作为第一电流电平的结果，在测试电路的参考节点和熔丝节点之间产生的差分信号; 使第二电流通过保险丝支脚和测试电路的参考支路，第二电平电流高于第一电流电平，以便能够以比与第一电平相比更低的值检测测试电路的跳闸电阻 尊重目前的一级; 以及作为所述第二电流电平的结果，检测在所述参考节点和所述测试电路的所述熔丝节点之间产生的差分信号。

公开(公告)号：US07307911B1

公开(公告)日：2007-12-11

申请号：US11460464

申请日：2006-07-27

申请人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

发明人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： An apparatus for sensing the state of a programmable resistive memory element device includes a latch device is coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg. The latch device is configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg. The fuse and reference resistance legs are further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

摘要翻译： 一种用于感测可编程电阻式存储元件器件的状态的装置包括一个锁存器件耦合到一个熔丝节点和一个参考节点，该熔断器节点包含在一个保险丝支脚内，而该参考节点配置在一个参考电阻支路内。 闩锁装置被配置为检测由于感测电流通过保险丝腿和参考电阻腿而导致在参考节点和熔丝节点之间产生的差分信号。 熔丝和参考电阻支腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流水平。

公开(公告)号：US08484543B2

公开(公告)日：2013-07-09

申请号：US13204929

申请日：2011-08-08

申请人： Darren L. Anand ,  Kevin W. Gorman ,  Michael R. Ouellette ,  Michael A. Ziegerhofer

发明人： Darren L. Anand ,  Kevin W. Gorman ,  Michael R. Ouellette ,  Michael A. Ziegerhofer

IPC分类号： H03M13/00

CPC分类号： G06F11/1048 ,  G11C17/165 ,  G11C29/027 ,  G11C2029/0411

摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.

摘要翻译： 选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。 可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。 每个状态机可以包括诸如“粘性位”的指示符，当其遇到类型的校正时可以被激活。 指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。

公开(公告)号：US07920003B1

公开(公告)日：2011-04-05

申请号：US12560593

申请日：2009-09-16

申请人： Darren L. Anand

发明人： Darren L. Anand

IPC分类号： H03K3/017

CPC分类号： H03K5/135 ,  H03K5/1565 ,  H03K2005/00052

摘要： A delay circuit with a delay equal to the percentage of the input pulse width is described. In one embodiment, the ratio of the discharge current to the charge-up current of a timing capacitor is used to determine the percentage of the input pulse width used for the output delay. In a first timing phase, the input pulse width is stored as a voltage on the timing capacitor. In a second timing phase, the output is delayed by a percentage of the input pulse width. In a third timing phase, the circuit is restored to the trip point to remove sensitivity to process variation or applied conditions variation such as voltage or temperature (P-V-T variation), and be ready for the next timing cycle.

摘要翻译： 描述延迟等于输入脉冲宽度百分比的延迟电路。 在一个实施例中，使用定时电容器的放电电流与充电电流的比率来确定用于输出延迟的输入脉冲宽度的百分比。 在第一定时相位中，将输入脉冲宽度作为电压存储在定时电容器上。 在第二定时阶段，输出延迟输入脉冲宽度的百分比。 在第三个定时阶段，电路恢复到跳变点，以消除对过程变化或应用条件变化（如电压或温度变化）（P-V-T变化）的敏感度，并准备下一个定时周期。

公开(公告)号：US20090063896A1

公开(公告)日：2009-03-05

申请号：US11849452

申请日：2007-09-04

申请人： Luis A. Lastras-Montano ,  Darren L. Anand ,  Jeffrey H. Dreibelbis ,  Charles A. Kilmer ,  Warren E. Maule ,  Robert B. Tremaine

发明人： Luis A. Lastras-Montano ,  Darren L. Anand ,  Jeffrey H. Dreibelbis ,  Charles A. Kilmer ,  Warren E. Maule ,  Robert B. Tremaine

IPC分类号： G06F11/16

CPC分类号： G11C29/76 ,  G11C11/401

摘要： A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.

摘要翻译： 一种用于通过设备外部的地址重映射提供DRAM设备级修复的系统和方法。 系统包括存储器控制器，其经由存储器模块具有到一个或多个存储器设备的接口。 存储器件包括可寻址冗余和非冗余存储器块。 存储器控制器还包括一种机构，用于经由存储器件外部的地址重新映射来代替一个或多个故障非冗余存储器块来利用一个或多个冗余存储器块。 重新映射发生在系统在线时。

公开(公告)号：US07453973B2

公开(公告)日：2008-11-18

申请号：US11533907

申请日：2006-09-21

申请人： Darren L. Anand ,  John R. Goss ,  Peter O. Jacobsen ,  Michael R. Ouellette ,  Thomas G. Sopchak ,  Donald L. Wheater

发明人： Darren L. Anand ,  John R. Goss ,  Peter O. Jacobsen ,  Michael R. Ouellette ,  Thomas G. Sopchak ,  Donald L. Wheater

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  G11C29/003

摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.

摘要翻译： 本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。 该电路包括连接到移位寄存器的输入和输出的选择器。 选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。 连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。 控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。 控制装置还包括从电路外部可访问的数据输出。 观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。 当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

公开(公告)号：US07315193B2

公开(公告)日：2008-01-01

申请号：US11161966

申请日：2005-08-24

申请人： Darren L. Anand ,  Larry Wissel

发明人： Darren L. Anand ,  Larry Wissel

IPC分类号： H01H37/76

CPC分类号： G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.

摘要翻译： 电路包括用于提供用于控制编程晶体管（212）的栅极的可变栅极信号（220）的电压控制器（224），其与编程集成电路的电可编程熔丝（“eFuse”）（204）一起使用 （200）。 电压控制器根据电路是否处于eFuse编程模式或eFuse电阻测量模式来调节门信号。 电压控制器可以可选地包括用于调谐门信号的电压调谐器（252），以解决由制造变化引起的编程晶体管的工作变化。

公开(公告)号：US07170299B1

公开(公告)日：2007-01-30

申请号：US11276120

申请日：2006-02-15

申请人： Darren L. Anand ,  Michael R. Ouellette ,  Troy J. Perry

发明人： Darren L. Anand ,  Michael R. Ouellette ,  Troy J. Perry

IPC分类号： H01H85/30 ,  H01H85/00 ,  G01R31/00

CPC分类号： G11C17/16 ,  G01R31/07 ,  G11C17/165 ,  G11C17/18 ,  G11C29/02 ,  G11C29/027 ,  G11C29/028 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system, method and program product for adjusting an environmental variable of a fuse blow of an electronic fuse are disclosed. A mimic NFET is coupled to a fuse blow source voltage line, a fuse blow gate voltage line, and a chip ground in the same manner as the electronic fuse, except that the mimic NFET is not attached to a poly fuse link. The on current (ion) and off current (ioff) of the mimic NFET are measured to determine a blow current of the electronic fuse. The environmental variable is adjusted based on the determined blow current.

摘要翻译： 公开了一种用于调整电子保险丝熔断器的环境变量的系统，方法和程序产品。 模拟NFET以与电子熔断器相同的方式耦合到保险丝熔断器电压线，保险丝熔断栅极电压线和芯片接地，除了模拟NFET未连接到多晶硅熔丝链路。 测量模拟NFET的导通电流（离子）和截止电流（ioff），以确定电子熔断器的吹扫电流。 环境变量根据确定的吹扫电流进行调整。

公开(公告)号：US06577156B2

公开(公告)日：2003-06-10

申请号：US09731147

申请日：2000-12-05

申请人： Darren L. Anand ,  John Edward Barth, Jr. ,  John Atkinson Fifield ,  Pamela Sue Gillis ,  Peter O. Jakobsen ,  Douglas Wayne Kemerer ,  David E. Lackey ,  Steven Frederick Oakland ,  Michael Richard Ouellette ,  William Robert Tonti

发明人： Darren L. Anand ,  John Edward Barth, Jr. ,  John Atkinson Fifield ,  Pamela Sue Gillis ,  Peter O. Jakobsen ,  Douglas Wayne Kemerer ,  David E. Lackey ,  Steven Frederick Oakland ,  Michael Richard Ouellette ,  William Robert Tonti

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  G11C29/802

摘要： A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.