公开(公告)号：US20060267112A1

公开(公告)日：2006-11-30

申请号：US11496452

申请日：2006-08-01

申请人： Satoshi Inaba ,  Makoto Fujiwara

发明人： Satoshi Inaba ,  Makoto Fujiwara

IPC分类号： H01L29/76

CPC分类号： H01L27/0924 ,  H01L21/28132 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A semiconductor device includes a first device region including a plurality of source regions and a plurality of drain regions of first conductivity type transistors, a plurality of loop-shaped gate electrode regions of the first conductivity type transistors, a second device region including a plurality of source regions and a plurality of drain regions of a second conductivity type transistors, a plurality of loop-shaped gate electrode regions of the second conductivity type transistors, a first wiring configured to supply a first voltage to at least one of the source regions of the first device region, a second wiring configured to supply a second voltage to at least one of the source regions of the second device region, and a third wiring electrically coupled to the drain regions of the first and second device regions and to the gate electrode regions of the first and the second conductivity type transistors.

摘要翻译： 半导体器件包括：第一器件区域，包括第一导电类型晶体管的多个源极区域和多个漏极区域;第一导电型晶体管的多个环形栅电极区域;第二器件区域， 源极区和第二导电型晶体管的多个漏极区，第二导电型晶体管的多个环形栅极电极区域，第一布线，被配置为向第一导电类型晶体管的源极区域中的至少一个 第一器件区域，被配置为向第二器件区域的源极区域中的至少一个提供第二电压的第二布线和电耦合到第一和第二器件区域的漏极区域和栅极电极区域的第三布线 的第一和第二导电类型的晶体管。

公开(公告)号：US20060166456A1

公开(公告)日：2006-07-27

申请号：US11388523

申请日：2006-03-25

申请人： Makoto Fujiwara ,  Kazunari Ishimaru ,  Akira Hokazono

发明人： Makoto Fujiwara ,  Kazunari Ishimaru ,  Akira Hokazono

IPC分类号： H01L21/20

CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/66818

摘要： A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).

摘要翻译： 形成FinFET的主要部分即散热片的半导体层具有在x方向上长且在y方向上短的形状。 翅片沿方向y的宽度在三个阶段上变化。 首先，在栅极长度为Lg的栅电极之间的沟道区域中，鳍方向y的宽度为Wch。 此外，与方向x上的通道区域相邻的源极/漏极扩展区域中的鳍状物的宽度方向是Wex​​t（> Wch）。 此外，与源极/漏极扩展区域相邻的源极/漏极区域中在方向x上的方向y上的鳍的宽度为Wsd（> Wext）。

公开(公告)号：US20060136749A1

公开(公告)日：2006-06-22

申请号：US11223939

申请日：2005-09-13

申请人： Tomoya Satou ,  Makoto Fujiwara ,  Kentarou Shiomi ,  Yusuke Nemoto ,  Yuishi Torisaki ,  Kazuya Shimizu ,  Shinji Inoue ,  Kazuya Fujimura ,  Makoto Ochi

发明人： Tomoya Satou ,  Makoto Fujiwara ,  Kentarou Shiomi ,  Yusuke Nemoto ,  Yuishi Torisaki ,  Kazuya Shimizu ,  Shinji Inoue ,  Kazuya Fujimura ,  Makoto Ochi

IPC分类号： H04L9/00 ,  G06F12/14 ,  H04L9/32 ,  G06F11/30

CPC分类号： G11B20/00086 ,  H04L9/0822 ,  H04L9/0833 ,  H04L9/0894 ,  H04L9/3236 ,  H04L2209/38 ,  H04L2209/60

摘要： In a target apparatus which stores at least one piece of domain key information in a first area and a plurality of pieces of content key information each associated with any one of the domain key information in a second area, a method for generating data for detecting tampering of the content key information. The method comprises the steps of encrypting the content key information associated with one of the domain key information using a chain encryption technique, extracting data at predetermined positions in the encrypted content key information, concatenating the pieces of data extracted at the predetermined positions in the encrypted content key information to obtain concatenated data, performing a hash calculation with respect to the concatenated data to obtain a hash value, storing check values corresponding to the data at the predetermined positions in plain text, in the target apparatus, and storing the hash value in the target apparatus.

摘要翻译： 在将第一区域中存储至少一段领域密钥信息和与第二区域中的任何一个域密钥信息相关联的多条内容密钥信息的目标设备中，存储用于检测篡改的数据的方法 的内容密钥信息。 该方法包括以下步骤：使用链式加密技术加密与一个领域密钥信息相关联的内容密钥信息，在加密的内容密钥信息中的预定位置提取数据，连接在加密的内容密钥信息中的预定位置提取的数据段 内容密钥信息以获得连接的数据，对所述连接的数据执行哈希计算以获得哈希值，将与所述预定位置上的数据相对应的校验值存储在目标设备中，并将哈希值存储在 目标设备。

公开(公告)号：US20050212040A1

公开(公告)日：2005-09-29

申请号：US10947405

申请日：2004-09-23

申请人： Akira Hokazono ,  Makoto Fujiwara

发明人： Akira Hokazono ,  Makoto Fujiwara

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the gate insulation film. A silicide film is formed on the gate electrode. First gate sidewall films are formed on side surfaces of the gate electrode. Second gate sidewall films are formed on the first gate sidewall films on the side surfaces of the gate electrode. First sidewall films are formed on side surfaces of the silicide film on the gate electrode. A source region and a drain region are formed on the semiconductor substrate so as to sandwich a channel region formed under the gate insulation film. Second sidewall films are formed on end portions of the first and second gate sidewall films formed on the source region and the drain region.

摘要翻译： 在半导体衬底上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 在栅电极上形成硅化物膜。 第一栅极侧壁膜形成在栅电极的侧表面上。 第二栅极侧壁膜形成在栅电极的侧表面上的第一栅极侧壁膜上。 第一侧壁膜形成在栅电极上的硅化物膜的侧表面上。 源极区域和漏极区域形成在半导体衬底上，以夹持形成在栅极绝缘膜下面的沟道区域。 第二侧壁膜形成在形成在源极区域和漏极区域上的第一和第二栅极侧壁膜的端部。

公开(公告)号：US5378781A

公开(公告)日：1995-01-03

申请号：US74520

申请日：1993-06-11

申请人： Makoto Fujiwara ,  Tadashi Amano

发明人： Makoto Fujiwara ,  Tadashi Amano

IPC分类号： C08F2/18 ,  C08F4/28 ,  C08F4/32 ,  C08F4/38 ,  C08F14/00 ,  C08F14/06 ,  C08F2/20

CPC分类号： C08F14/06

摘要： A process for producing a vinyl chloride polymer comprises subjecting a vinyl chloride monomer or a mixture comprising a major proportion of a vinyl chloride monomer along with at least one co-polymerizable monomer to suspension polymerization in an aqueous medium in the presence of a monomer-soluble polymerization initiator. The monomer-soluble polymerization initiator comprises, in combination, (A) a compound which is free of a benzene ring, a cyclohexyl group and an alkoxy group in the molecule and whose 10 hours half-life temperature at a concentration of 0.1 mole/liter of benzene is in the range of 30.degree. to 50.degree. C. and (B) 1-cyclohexyl-1-methylethyl peroxyneodecanoate.

摘要翻译： 一种制备氯乙烯聚合物的方法包括使氯乙烯单体或包含大部分氯乙烯单体的混合物与至少一种可共聚单体一起在水性介质中在单体可溶的存在下进行悬浮聚合 聚合引发剂。 单体可溶性聚合引发剂组合包含（A）分子中不含苯环，环己基和烷氧基的化合物，其浓度为0.1摩尔/升的10小时半衰期温度 的苯在30〜50℃的范围内，（B）过氧化新癸酸1-环己基-1-甲基乙酯。

公开(公告)号：US08774575B2

公开(公告)日：2014-07-08

申请号：US13132735

申请日：2009-12-01

申请人： Makoto Fujiwara ,  Kenji Miyao ,  Yoji Shirato ,  Koji Choki ,  Mutsuhiro Matsuyama

发明人： Makoto Fujiwara ,  Kenji Miyao ,  Yoji Shirato ,  Koji Choki ,  Mutsuhiro Matsuyama

IPC分类号： G02B6/26

CPC分类号： G02B6/4214 ,  G02B6/1221 ,  G02B6/138

摘要： An optical waveguide includes a clad layer, a core layer and a clad layer which are laminated together in this order from a lower side thereof. Within the core layer, a core portion and a side clad portion provided adjacent to the core portion so as to surround side surfaces of the core portion are formed. Further, a part of the side clad portion prevents a left side end of the core portion from being exposed outside. A mirror formation region is constituted from a region consisting of such a part of the side clad portion and a part of each of the clad layers located thereabove and therebelow. This mirror formation region is subjected to digging processing so that a concave portion is formed. An inner surface of this concave portion serves as the mirror. From the mirror, a material other than a material constituting the core portion, that is, a material constituting each of the clad layers and a material constituting the side clad portion are exposed.

摘要翻译： 光波导包括从其下侧依次层叠在一起的包覆层，芯层和覆盖层。 在芯层内，形成与芯部相邻设置以包围芯部的侧面的芯部和侧包层部。 此外，侧包层部分的一部分防止芯部的左侧端部暴露在外部。 镜形成区域由侧包层部分的一部分和位于其上方和下方的每个包覆层的一部分构成的区域构成。 对该镜面形成区域进行挖掘处理，形成凹部。 该凹部的内表面用作反射镜。 从镜子来看，除了构成芯部的材料以外的材料，即构成每个包覆层的材料和构成侧包层部分的材料都被露出。

公开(公告)号：US20130182997A1

公开(公告)日：2013-07-18

申请号：US13824766

申请日：2011-09-22

申请人： Makoto Fujiwara ,  Motoya Kaneta

发明人： Makoto Fujiwara ,  Motoya Kaneta

IPC分类号： G02B6/12

CPC分类号： G02B6/12004 ,  G02B6/4214

摘要： An object of the present invention is to provide an optical waveguide module which has a small optical coupling loss between the light element and the optical waveguide and can perform high-quality optical communication, a method for producing the optical waveguide module with high efficiency, and an electronic apparatus which includes the optical waveguide module and can perform high-quality optical communication, and the present invention provides an optical waveguide module including: an optical waveguide including a core portion, a clad portion that is provided to cover a side surface of the core portion, and an optical path-converting unit that is provided partway along the core portion or on an extended line of the core portion and that converts an optical path of the core portion to the outside of the clad portion; an optical element that is provided over the clad portion; a circuit board that is provided between the optical waveguide and the optical element and has a through-hole formed along an optical path connecting between the optical path-converting unit and the optical element; and a sealing portion that is transparent and is formed in a gap between the optical element and the circuit board; wherein a part of the sealing portion is inserted into the through-hole, and an inserted portion of the sealing portion functions as a lens for converging signal light passing though the optical path.

摘要翻译： 本发明的目的是提供一种在光元件和光波导之间具有小的光耦合损耗并且可以执行高质量光通信的光波导模块，一种高效率地制造光波导模块的方法，以及 一种包括光波导模块并且可以执行高质量光通信的电子设备，并且本发明提供一种光波导模块，其包括：光波导，包括芯部分，覆盖部分被设置为覆盖所述光波导模块的侧表面 芯部分和光路转换单元，其沿核心部分或芯部的延伸线设置一半，并且将芯部的光路转换到包层部分的外部; 设置在所述包层部上的光学元件; 电路板，设置在所述光波导与所述光学元件之间，并具有沿着连接在所述光路转换单元与所述光学元件之间的光路形成的通孔; 以及密封部，其是透明的并且形成在所述光学元件和所述电路板之间的间隙中; 其中所述密封部分的一部分插入所述通孔中，并且所述密封部分的插入部分用作用于会聚通过所述光路的信号光的透镜。

公开(公告)号：US20130177277A1

公开(公告)日：2013-07-11

申请号：US13824816

申请日：2011-09-27

申请人： Makoto Fujiwara ,  Tsuyoshi Furukawa ,  Shinsuke Terada ,  Motoya Kaneta

发明人： Makoto Fujiwara ,  Tsuyoshi Furukawa ,  Shinsuke Terada ,  Motoya Kaneta

IPC分类号： G02B6/32 ,  G02B6/34

CPC分类号： G02B6/32 ,  G02B6/34 ,  G02B6/4206 ,  G02B6/4214 ,  G02B6/43

摘要： An object is to provide an optical waveguide that has low optical coupling loss when optically coupled with an optical element and that is capable of performing high-quality optical communication, a method for efficiently producing the optical waveguide, an optical waveguide module that is provided with the optical waveguide and is capable of performing high-quality optical communication, a method for efficiently producing the optical waveguide module, and an electronic apparatus. Provided is an optical waveguide including: a core portion; a clad portion that is provided to cover a side surface of the core portion; an optical path-converting unit that is provided partway along the core portion or on an extended line of the core portion and that converts an optical path of the core portion to the outside of the clad portion; and a lens that is provided on a surface of the clad portion at least at a portion optically connected to the core portion via the optical path-converting unit, and that is formed by causing the surface to locally protrude or to be locally depressed.

摘要翻译： 本发明的目的是提供一种与光学元件光学耦合并且能够进行高质量的光通信时具有低光耦合损耗的光波导，用于有效地产生光波导的方法，设置有光波导的光波导模块 光波导，能够进行高质量的光通信，有效地生产光波导模块的方法和电子设备。 提供一种光波导，包括：芯部; 设置成覆盖所述芯部的侧面的包层部; 光路转换单元，其沿芯部的一部分或芯部的延长线设置，并且将芯部的光路转换到包层部的外侧; 以及透镜，其经由光路转换单元至少在与芯部光学连接的部分处设置在包层部分的表面上，并且通过使表面局部突出或局部凹陷而形成。

公开(公告)号：US08407488B2

公开(公告)日：2013-03-26

申请号：US13091882

申请日：2011-04-21

申请人： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

发明人： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

IPC分类号： G06F12/14 ,  H04L9/00

CPC分类号： G06F21/72 ,  G06F9/4401 ,  G06F21/123 ,  G06F21/85 ,  G06F2221/2105

摘要： A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

公开(公告)号：US08299988B2

公开(公告)日：2012-10-30

申请号：US12335264

申请日：2008-12-15

申请人： Yoshihiro Oishi ,  Makoto Fujiwara

发明人： Yoshihiro Oishi ,  Makoto Fujiwara

IPC分类号： G09G3/32

CPC分类号： H05B33/0827 ,  H05B33/0815 ,  H05B33/0818 ,  Y02B20/346

摘要： A pulse signal delay circuit comprises: a first pulse edge delay circuit for generating a first delay timing signal for sequentially outputting a first edge detection delay timing gained by detecting the rising edge of an input pulse signal and delaying the detection timing by a constant delay time a predetermined number of times; a second pulse edge delay circuit for generating a second delay timing signal for sequentially outputting a second edge detection delay timing gained by detecting the falling edge of the input pulse signal and delaying the detection timing by the delay time the number of times; and a delay pulse signal generating circuit for generating and outputting delay pulse signals rising and falling according to the first and second edge detection delay timings, respectively, from the first and second delay timing signals, the first and second edge detection delay timings delayed the same number of times.

摘要翻译： 一种脉冲信号延迟电路，包括：第一脉冲沿延迟电路，用于产生第一延迟定时信号，用于顺序地输出通过检测输入脉冲信号的上升沿并延迟检测定时一定的延迟时间而获得的第一边沿检测延迟定时 预定次数; 第二脉冲边缘延迟电路，用于产生第二延迟定时信号，用于顺序地输出通过检测输入脉冲信号的下降沿并将检测定时延迟延迟时间的次数而获得的第二边缘检测延迟定时; 以及延迟脉冲信号发生电路，用于分别根据第一和第二延迟定时信号产生和输出根据第一和第二边缘检测延迟定时的上升和下降的延迟脉冲信号，第一和第二边缘检测延迟定时将相同延迟 次数。