公开(公告)号：US08030151B2

公开(公告)日：2011-10-04

申请号：US12382966

申请日：2009-03-27

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea

IPC: H01L21/8238

CPC classification number: H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

Abstract: A bipolar transistor (101) has a base (243) formed with an intrinsic base portion (2431), a base contact portion (245C), and a base link portion (243L) that extends between the intrinsic base portion and the base contact portion. An isolating dielectric layer (267-1 or 267-2) is provided above the base link portion. The length of the base link portion is determined, and thereby controlled, with a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, provided on the dielectric layer above the base link portion. The lateral spacing portion is typically provided as part of a layer of non-monocrystalline semiconductor material used in the gate electrode of an insulated-gate field-effect transistor.

Abstract translation: 双极晶体管（101）具有形成有本征基部（2431），基部接触部（245C）和基部连接部（243L）的基部（243），该基部连接部在本征基部与基部接触部 。 隔离介质层（267-1或267-2）设置在基座连接部分上方。 确定基部连接部分的长度，从而通过设置在基底连接件上方的电介质层上的大部分非单晶半导体材料（优选多晶半导体材料）的横向间隔部分（269-1或269-2）进行控制 一部分。 横向间隔部分通常被提供作为在绝缘栅场效应晶体管的栅电极中使用的非单晶半导体材料层的一部分。

公开(公告)号：US08013390B1

公开(公告)日：2011-09-06

申请号：US12940000

申请日：2010-11-04

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US07785971B1

公开(公告)日：2010-08-31

申请号：US11703350

申请日：2007-02-06

Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L21/336

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: Fabrication of complementary first and second insulated-gate field-effect transistors (110 or 112 and 120 or 122) from a semiconductor body entails separately introducing (i) three body-material dopants into the body material (50) for the first transistor so as to reach respective maximum dopant concentrations at three different locations in the first transistor's body material and (ii) two body-material dopants into the body material (130) for the second transistor so as to reach respective maximum dopant concentrations at two different locations in the second transistor's body material. Gate electrodes (74 or 94 and 154 or 194) are subsequently defined after which source/drain zones (60, 62 or 80, 82 and 140, 142 or 160, 162) are formed in the semiconductor body. The vertical dopant profiles resulting from the body-material dopants alleviate punchthrough and reduce current leakage.

Abstract translation: 从半导体主体制造互补的第一和第二绝缘栅场效应晶体管（110或112和120或122）需要将（i）三个体材料掺杂物分别引入用于第一晶体管的体材料（50）中，以便 以在第一晶体管主体材料中的三个不同位置处达到各自的最大掺杂浓度，和（ii）两个体材料掺杂物进入用于第二晶体管的主体材料（130）中，以便达到第二晶体管的两个不同位置处的各自的最大掺杂浓度 第二晶体管的主体材料。 随后在半导体本体中形成源/漏区（60,62或80,82和140,142或160,162）之后限定栅电极（74或94和154或194）。 由体材料掺杂物产生的垂直掺杂剂分布减轻穿透并减少电流泄漏。

公开(公告)号：US20080311717A1

公开(公告)日：2008-12-18

申请号：US11981355

申请日：2007-10-31

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material is preferably provided with a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 制造绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480） 以便具有低于其源极/漏极区的一个（104或264）的低破坏垂直掺杂剂轮廓，用于减小沿着该源极/漏极区与邻接主体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地设置有沿着另一个源极/漏极区（102或262）设置的更加重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US07145191B1

公开(公告)日：2006-12-05

申请号：US10922035

申请日：2004-08-18

Applicant: Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L29/76

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion.

Abstract translation: p沟道IGFET（120或122）的源极/漏极区（140和142或160和162）具有渐变结特征以减小结电容，从而提高开关速度。 每个源极/漏极区域包含主要部分（140M，142M，160M，或162M）和较轻掺杂的下部分（140L，142L，160L或162L），并且垂直连续 ，主要部分。

公开(公告)号：US07078787B1

公开(公告)日：2006-07-18

申请号：US10699221

申请日：2003-10-31

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/93

CPC classification number: H01L27/0808 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

Abstract: A semiconductor junction varactor is designed with gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-point threshold voltages for enabling the varactor capacitance to vary relatively gradually with a control voltage applied to the varactor.

Abstract translation: 半导体结变容二极管设计有门增强，使变容二极管能够实现最大电容与最小电容的高比率。 变容二极管具有被分成不同零点阈值电压的多个部分的栅极区域（131或181），以使变容二极管电容随施加到变容二极管的控制电压相对逐渐变化。

公开(公告)号：US06548842B1

公开(公告)日：2003-04-15

申请号：US09540442

申请日：2000-03-31

Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L2994

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/665

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Abstract translation: IGFET（40或42）具有位于主体材料（50）中的通道区（64或84）。 通过设置通道区域中的净掺杂剂浓度以在IGFET的源极/漏极区域（60和62或80和82）之间的位置处纵向达到局部表面最小值来减轻短通道阈值电压滚降和穿透，以及 通过布置主体材料中的净掺杂剂浓度达到主体材料深度超过0.1μm的局部地下最大深度，但不超过0.4μm的主体材料深度。

公开(公告)号：US5897355A

公开(公告)日：1999-04-27

申请号：US951839

申请日：1997-10-16

Applicant: Constantin Bulucea ,  Richard A. Blanchard

Inventor： Constantin Bulucea ,  Richard A. Blanchard

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/7802 ,  H01L29/7808 ,  H01L29/0626 ,  H01L29/1095 ,  Y10S438/965

Abstract: An insulated gate field effect transistor is manufactured according to a process in which an insulated gate structure is formed along a semiconductor chip. Dopant is introduced into the chip to form a body region, semiconductor material outside the body region forming a drain region. Dopant is introduced into the chip at the location of part of the body region to form a source region spaced apart from the drain region by a channel region. Dopant of the same conductivity type as the body-region dopant is introduced through a dopant-introducing section of the chip's upper surface and into the chip at the location of part of the body region to form a sub-surface peaked portion of the body region, the dopant-introducing section being spaced laterally apart from the channel and source regions. The sub-surface peaked portion reaches a peak net dopant concentration below the chip's upper surface so as to improve the transistor's ruggedness under drain avalanche conditions.

Abstract translation: 根据沿着半导体芯片形成绝缘栅极结构的工艺制造绝缘栅场效应晶体管。 将掺杂剂引入芯片中以形成体区域，形成漏极区域的体区外的半导体材料。 掺杂剂在身体区域的一部分的位置被引入到芯片中，以形成通过沟道区域与漏极区域间隔开的源极区域。 与身体区域掺杂剂相同的导电类型的掺杂剂通过芯片的上表面的掺杂剂引入部分引入到体区的部分位置处的芯片中，以形成体区的亚表面峰部分 掺杂物引入部分与沟道和源极区域横向间隔开。 亚表面峰部分达到峰值净掺杂剂浓度低于芯片的上表面，以便在漏极雪崩条件下提高晶体管的耐用性。

公开(公告)号：US5866931A

公开(公告)日：1999-02-02

申请号：US777636

申请日：1996-12-31

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/0696 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/7802

Abstract: Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well.

Abstract translation: 公开了两个拓扑不同的单元，其减少了每个器件的总触点数，并且适用于中高压DMOS晶体管。 这些细胞使用源和身体之间的集成连接，使得它们对于通过颗粒污染或光刻缺陷接触接触不那么敏感。 这些拓扑结构包括细长的六角形细胞或埋深体细胞。 两个电池在高电流中压沟槽DMOS晶体管中是最有效的，其中身体接触的密度变得过高，而周边/面积几何因子不太重要。 所公开的实施例是DMOS结构的沟槽类型。 然而，这些单元也可以在平面DMOS晶体管中实现。

公开(公告)号：US5384477A

公开(公告)日：1995-01-24

申请号：US28456

申请日：1993-03-09

Applicant: Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

Inventor： Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0921 ,  Y10S148/023 ,  Y10S438/904 ,  Y10S438/917

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior Which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract translation: 描述了抑制CMOS结构中的闭锁的独特方法。 可以植入在硅中显示中等水平并满足局部作用和电相容性标准的原子物质，以抑制引起闭锁的寄生双极性行为。 通过CMOS结构在有源MOS器件区域之外的临界寄生双极区域可以实现少数载流子寿命的降低。 实现这一目标的一个方法是在源极/漏极掺杂剂被植入之前，使用源极/漏极掩模来局部注入少数载流子寿命衰减器（MCLR）。 这允许MCLR在n沟道晶体管和p沟道晶体管的不同深度或者甚至不同的物种中被引入。 实现这一目标的另一种方法是要求在隔离氧化，栅极氧化或活性阈值植入完成之前，在该过程中非常早地完成覆盖MCLR植入物。