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公开(公告)号：US08832393B2
公开(公告)日：2014-09-09
申请号：US13449684
申请日：2012-04-18
申请人： Jung Ho Cho , Vladimir Sindalovsky , Lane A. Smith
发明人： Jung Ho Cho , Vladimir Sindalovsky , Lane A. Smith
CPC分类号： G06F1/12 , G06F5/065 , G06F5/14 , G06F2205/066
摘要： In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO read clock stoppage signal is generated by master logic that stops the read clock shared by all the transmit channels and then re-starts the read clock to align them. The FIFO read clock stoppage signal is applied to the read clock of all FIFOs which need to be aligned and, when rate change is needed, the FIFO read clock stoppage signal suspends the read clock, causing local write and read pointers to be reset. After the FIFO read clock stoppage signal is de-asserted, the read clock starts to all FIFOs concurrently, thereby aligning the channels.
摘要翻译： 在所描述的实施例中，多个先入先出的缓冲指针（多FIFO指针）对准系统包括同步电路以对准多个FIFO缓冲器操作。 FIFO读时钟停止信号由主逻辑产生，停止所有发送通道共享的读时钟，然后重新启动读时钟对齐它们。 FIFO读时钟停止信号被施加到需要对齐的所有FIFO的读时钟上，并且当需要速率改变时，FIFO读时钟停止信号暂停读时钟，导致本地写指针和读指针被复位。 在FIFO读取时钟停止信号被取消断言之后，读取时钟同时开始到所有FIFO，从而对齐信道。
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公开(公告)号：US08687756B2
公开(公告)日：2014-04-01
申请号：US13235628
申请日：2011-09-19
IPC分类号： H03D3/24
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.
摘要翻译： 在所描述的实施例中，接收机包括具有比例和积分环路控制的压控振荡器（VCO）的时钟和数据恢复（CDR）电路，以及使用相位和频率检测器（PFD）控制的锁定到参考（L2R）模式电路 在没有输入数据到CDR的情况下。 在没有到CDR的输入数据的情况下，结合PFD的PFD控制的常规CDR二阶循环与基于操作的基于参考操作的锁相比，实现了相对较快的锁定参考。
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83.发明授权Method and apparatus for generating early or late sampling clocks for CDR data recovery 有权用于生成用于CDR数据恢复的早期或晚期采样时钟的方法和装置公开(公告)号：US08407511B2
公开(公告)日：2013-03-26
申请号：US12199904
申请日：2008-08-28
CPC分类号： H04L7/0337
摘要： Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.
摘要翻译： 提供了用于CDR数据采样的时钟相位发生器的方法和装置，其相对于理想的转换和采样点产生早和/或晚的采样时钟。 通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生早期采样时钟; 以及延迟所述转换时钟信号中的至少一个以产生一个或多个早期时钟信号。 通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生延迟采样时钟; 以及延迟所述数据采样时钟信号中的至少一个以产生一个或多个后期时钟信号。 早期的时钟信号可以用于例如基于阈值的判决反馈均衡器中。 后期时钟信号可以用于例如经典的判决反馈均衡器中。
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公开(公告)号：US08388009B1
公开(公告)日：2013-03-05
申请号：US13114494
申请日：2011-05-24
申请人： Lane A. Smith
发明人： Lane A. Smith
IPC分类号： B62H1/08
CPC分类号： B62H1/08
摘要： A two-wheeled vehicle comprising a frame, a pair of wheels, and a pedal assembly. The pedal assembly has a sprocket, right crank arm assembly and a left crank arm assembly (the crank arm assemblies include pedals), wherein at least one of the two crank arm assemblies comprises an outer member and an inner member, typically, the inner member being cylindrical at least partially telescopically received in the outer member. Typically one of the inner or outer member is moveable, telescopically between a retracted locked, fixed position and an extended locked, fixed position. In the extended position, the two members lock with respect to each other and allow the bicycle or other two-wheeled vehicle to lay adjacent the support surface on the removed end of the extended member, which extended member typically contains the pedal portion of the pedal assembly.
摘要翻译： 一种包括框架，一对车轮和踏板组件的两轮车辆。 踏板组件具有链轮，右曲柄臂组件和左曲柄臂组件（曲柄组件包括踏板），其中两个曲柄臂组件中的至少一个包括外部构件和内部构件，通常为内部构件 至少部分地可伸缩地容纳在外部构件中的圆柱形。 通常，内部构件或外部构件中的一个可伸缩地在缩回的锁定的固定位置和延伸的锁定的固定位置之间可移动。 在延伸位置，两个构件相对于彼此锁定并允许自行车或其他两轮车辆邻近支撑表面放置在延伸构件的移除端上，该延伸构件通常包含踏板的踏板部分 部件。
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85.发明授权Methods and apparatus for detecting a loss of lock condition in a clock and data recovery system 有权用于检测时钟和数据恢复系统中锁定状况的损失的方法和装置公开(公告)号：US08208521B2
公开(公告)日：2012-06-26
申请号：US11967632
申请日：2007-12-31
IPC分类号： H04B17/00
CPC分类号： H04L7/0062 , H04L7/0083
摘要： Methods and apparatus are provided for detecting a loss of lock condition in a clock and data recovery system. A loss of lock condition is detected in a clock and data recovery system that generates a recovered clock signal from a received signal by sampling the received signal for a plurality of different phases using one or more latches clocked by the recovered clock; evaluating the samples to monitor a data eye associated with the received signal; and detecting the loss of lock condition if the data eye does not satisfy one or more predefined conditions. Generally, the predefined conditions identify a loss of the data eye (e.g., when the data eye cannot be substantially detected), for example, based on a degree of opening of the data eye. The clock and data recovery system can optionally be restarted if the loss of lock condition is detected.
摘要翻译： 提供了用于检测时钟和数据恢复系统中的锁定状况的损失的方法和装置。 在时钟和数据恢复系统中检测到锁定状态的损失，该系统通过使用由恢复时钟计时的一个或多个锁存器对接收到的信号进行多个不同相位的采样来产生来自接收信号的恢复时钟信号; 评估样本以监测与接收信号相关联的数据眼; 并且如果数据眼不满足一个或多个预定条件，则检测锁定条件的损失。 通常，预定义的条件识别数据眼睛的损失（例如，当不能基本上检测到数据眼时），例如，基于数据眼睛的打开程度。 如果检测到锁定状态的丢失，则可以重新启动时钟和数据恢复系统。
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公开(公告)号：US08046481B2
公开(公告)日：2011-10-25
申请号：US12610462
申请日：2009-11-02
IPC分类号： G06F15/16
CPC分类号： H04L12/2838 , H04L69/03 , H04L69/32
摘要： A conventional serial communications protocol that is limited to supporting only host-to-slave communications, such as SATA or SAS, is extended to support peer-to-peer communications, e.g., by adding a memory-map layer into the conventional protocol stack between the link layer and the protocol layer. The addition of the memory-map layer enables two (or more) non-host devices (i.e., peer devices) to communicate with one another without using a host computer and without relying on conventional protocol-bridging techniques.
摘要翻译： 仅限于支持诸如SATA或SAS的主机到从机通信的常规串行通信协议被扩展以支持对等通信，例如通过将存储器映射层添加到常规协议栈之间 链路层和协议层。 存储器映射图层的添加使得两个（或多个）非主机设备（即，对等设备）彼此通信，而不使用主计算机，而不依赖于传统的协议桥接技术。
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87.发明授权公开(公告)号：US07995743B2
公开(公告)日：2011-08-09
申请号：US11534918
申请日：2006-09-25
IPC分类号： H04M3/00
CPC分类号： H04M3/2272 , H04M3/14
摘要： The invention provides a low cost, simple, circuit for detecting the condition of a telephone line.
摘要翻译： 本发明提供了一种用于检测电话线条件的低成本，简单的电路。
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88.发明授权公开(公告)号：US07923868B2
公开(公告)日：2011-04-12
申请号：US12012761
申请日：2008-02-05
IPC分类号： H02J3/00
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译： 公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。 该电路包括一个锁存器和一个处理器。 锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。
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89.发明授权Method and apparatus for decision-feedback equalization using single-sided eye with global minimum convergence 有权使用具有全局最小收敛的单面眼的判决反馈均衡的方法和装置公开(公告)号：US07720142B2
公开(公告)日：2010-05-18
申请号：US11686148
申请日：2007-03-14
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： Methods and apparatus are provided for decision-feedback equalization with global minimum convergence. A threshold position of one or more DFE latches employed by a decision-feedback equalizer is determined by obtaining a plurality of samples of a single-sided data eye using at least one decision latch and at least one roaming latch; comparing the samples obtained by the at least one decision latch and at least one roaming latch to identify an upper and lower voltage boundary of the single-sided data eye; and determining a threshold position of the one or more DFE latches based on the upper and lower voltage boundaries. The comparison can optionally comprise obtaining an exclusive or (XOR) of the samples obtained by the at least one decision latch and at least one roaming latch. The XOR comparison positions an opening for the single-sided data eye at a zero hit count.
摘要翻译： 提供了用于具有全局最小收敛的判决反馈均衡的方法和装置。 通过使用至少一个判定锁存器和至少一个漫游锁存器获得单面数据眼睛的多个采样来确定由判决反馈均衡器采用的一个或多个DFE锁存器的阈值位置; 将由所述至少一个判定锁存器获得的样本和至少一个漫游锁存器进行比较，以识别所述单侧数据眼睛的上下电压边界; 以及基于所述上下电压边界确定所述一个或多个DFE锁存器的阈值位置。 比较可以可选地包括获得由至少一个决定锁存器和至少一个漫游锁存器获得的样本的异或（XOR）。 XOR比较将零点击数的单面数据眼的开口位置。
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90.发明授权公开(公告)号：US07696800B2
公开(公告)日：2010-04-13
申请号：US12012758
申请日：2008-02-05
IPC分类号： H03K5/12
CPC分类号： H03K5/02 , H03K5/06 , H03K19/017581 , H04L25/0288
摘要： Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.
摘要翻译： 公开了一种通过通信信道（例如，线，背板等）调整从发射机发射到接收机的信号的特性的电路。 该电路包括一个锁存器，该锁存器在阈值电压施加到锁存器之后多次接收电路中预定点处的信号并对信号的电压进行多次采样。 该电路还包括一个处理器，当采样电压指示转换点时，确定信号的特性，并且当采样电压不指示转换点时调整阈值电压。 当信号的特性在预定范围之外时，处理器通过调节发射机的电流和电压中的至少一个来调整信号的特性。
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