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公开(公告)号：US20060125493A1
公开(公告)日：2006-06-15
申请号：US11008937
申请日：2004-12-13
IPC分类号： G01R27/08
CPC分类号： G01N17/04
摘要： A method of monitoring corrosion and corrosion sensor includes a first element including a corrodible element to be exposed to a corrosive or corrosion-suspect environment, and a second element including a corrosion sensing circuit coupled with the corrodible element for generating a wireless signal based on the corrosion of the corrodible element.
摘要翻译： 监测腐蚀和腐蚀传感器的方法包括第一元件，其包括暴露于腐蚀性或腐蚀性可疑环境的可腐蚀元件，以及包括与可腐蚀元件耦合的腐蚀感测电路的第二元件，用于基于 可腐蚀元素的腐蚀。
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82.发明授权Vertically stacked field programmable nonvolatile memory and method of fabrication 有权垂直堆叠现场可编程非易失性存储器和制造方法公开(公告)号：US06780711B2
公开(公告)日：2004-08-24
申请号：US10253354
申请日：2002-09-23
IPC分类号： H01L21336
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译： 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。
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83.发明授权Multigate semiconductor device with vertical channel current and method of fabrication 失效具有垂直沟道电流的半导体器件和制造方法公开(公告)号：US06677204B2
公开(公告)日：2004-01-13
申请号：US10254878
申请日：2002-09-26
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , G11C11/5621 , G11C11/5671 , G11C16/0458 , G11C16/0475 , G11C2211/5611 , G11C2211/5612 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface.
摘要翻译： 本发明是一种多位非易失性存储器及其制造方法。 根据本发明，形成具有第一和第二通道表面的硅通道体。 在第一通道表面附近形成电荷存储介质，并且在第二通道表面附近形成第二电荷存储介质。 与第一通道表面相邻的第一电荷存储介质相邻地形成第一控制栅极，并且邻近第二表面邻近第二电荷存储介质形成第二控制栅极。
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公开(公告)号：US06627530B2
公开(公告)日：2003-09-30
申请号：US09746204
申请日：2000-12-22
IPC分类号： H01L214763
CPC分类号： H01L27/0688 , H01L21/32135 , H01L21/8221 , H01L27/1214 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration between a first signal line and a second signal line, where the two signal lines comprise similar materials. The method includes selectively patterning the second signal line material and the circuit without patterning the first signal line. One way the second signal line is patterned without patterning the first signal line is by modifying the etch chemistry. A second way the second signal line is patterned without patterning the first signal line is by including an etch stop between the first signal line and the second signal line. The invention is also directed at targeting a desired edge angle of a stacked circuit structure. In terms of patterning techniques, a desired edge angle is targeted by modifying, for example, the etch chemistry from one that is generally anisotropic to one that has a horizontal component to achieve an edge angle that is slightly re-entrant (i.e., having negative slope).
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公开(公告)号：US06624011B1
公开(公告)日：2003-09-23
申请号：US09639750
申请日：2000-08-14
IPC分类号： H01L2100
CPC分类号： H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Postponing at least some thermal processing operations, as multiple levels of a three dimensional circuit are formed.
摘要翻译： 当形成三维电路的多个级别时，推迟至少一些热处理操作。
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86.发明授权Multigate semiconductor device with vertical channel current and method of fabrication 有权具有垂直沟道电流的半导体器件和制造方法公开(公告)号：US06580124B1
公开(公告)日：2003-06-17
申请号：US09639577
申请日：2000-08-14
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , G11C11/5621 , G11C11/5671 , G11C16/0458 , G11C16/0475 , G11C2211/5611 , G11C2211/5612 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface.
摘要翻译： 本发明是一种多位非易失性存储器及其制造方法。 根据本发明，形成具有第一和第二通道表面的硅通道体。 在第一通道表面附近形成电荷存储介质，并且在第二通道表面附近形成第二电荷存储介质。 与第一通道表面相邻的第一电荷存储介质相邻地形成第一控制栅极，并且邻近第二表面邻近第二电荷存储介质形成第二控制栅极。
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公开(公告)号：US06483736B2
公开(公告)日：2002-11-19
申请号：US09939431
申请日：2001-08-24
IPC分类号： G11C1100
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
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公开(公告)号：US6034882A
公开(公告)日：2000-03-07
申请号：US192883
申请日：1998-11-16
IPC分类号： H01L27/10 , G11C11/56 , G11C17/16 , H01L27/102 , G11C17/00
CPC分类号： H01L27/1021 , G11C11/5692 , G11C13/003 , G11C17/16 , G11C11/5678 , G11C2213/71 , G11C2213/76
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
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