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    Measuring device and method for measuring relative phase shifts of digital signals
    82.
    发明申请
    Measuring device and method for measuring relative phase shifts of digital signals 有权
    用于测量数字信号相对相移的测量装置和方法

    公开(公告)号：US20070226602A1

    公开(公告)日：2007-09-27

    申请号：US11530257

    申请日：2006-09-08

    Applicant: Stephane Kirmser ,  Heinz Mattes ,  Sebastian Sattler

    Inventor： Stephane Kirmser ,  Heinz Mattes ,  Sebastian Sattler

    IPC: G06F11/00

    CPC classification number: G01R31/31711 ,  G01R25/00 ,  G01R31/31725

    Abstract: M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tsig long. The test signal is sampled with N sampled values at a sampling frequency fs=1/Ts. Also, N*Ts=M*Tsig, where N>M. The sampled values are numbered progressively by n, for which 0≦n ≦N−1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift Tφ is calculated by ∑ i = 0 M - 1 ⁢   ⁢ Idx ⁡ ( i ) + K , K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising or only falling zero crossings are taken into account.

    Abstract translation: 接收测试信号和参考信号的M个周期。 在每种情况下，测试信号和参考信号的周期都是长的。 测试信号以采样频率f N 1 = 1 / T S N的采样值采样。 此外，N * T S = M * T S，其中N> M。 采样值逐渐被n编号，0 <= n <= N-1。 采样值相对于参考信号具有限定的相对相移。 相位偏移T 由 < MUNDEROVER> Σ i = 0 MI> - 1 > Idx ⁡ （ i MO> + K ， K为常数，Idx（i）对应于在参考信号的第i个时段期间的测试信号过零之后的第一采样值或最后采样值的数量n 在参考信号的第i个周期之前的测试信号过零之前。 只考虑上升或下降的零交叉点。

      Calibrated differential voltage crossing
      83.
      发明授权
      Calibrated differential voltage crossing 失效

      公开(公告)号：US07152008B2

      公开(公告)日：2006-12-19

      申请号：US11013255

      申请日：2004-12-15

      Applicant: John F. Zumkehr ,  James E. Chandler ,  Renjeng Chiang

      Inventor： John F. Zumkehr ,  James E. Chandler ,  Renjeng Chiang

      IPC: G01R35/00 ,  G06F19/00

      CPC classification number: G01R25/00

      Abstract: In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a receiver pair to receive a differential signal and a reference signal and to generate at least one comparison signal reflecting where a first signal of the differential signal and a second signal of the differential signal cross each other with respect to the reference signal. The second signal is a negative compliment of the first signal. The apparatus further includes a phase detector to determine a phase error based on the at least one comparison signal. The apparatus also includes an edge delay control driver pair to adjust the differential signal based on the phase error.

      Module, system and method for testing a phase locked loop
      84.
      发明授权
      Module, system and method for testing a phase locked loop 失效
      用于测试锁相环的模块，系统和方法

      公开(公告)号：US07023195B2

      公开(公告)日：2006-04-04

      申请号：US10670683

      申请日：2003-09-25

      Applicant: Yair Rosenbaum ,  Sergey Sofer ,  Emil Yehushua

      Inventor： Yair Rosenbaum ,  Sergey Sofer ,  Emil Yehushua

      IPC: G01R23/12 ,  H03D3/24

      CPC classification number: G01R29/26 ,  G01R25/00

      Abstract: A digital test module (5) is provided for testing a phase locked loop circuit. The module (5) includes phase detection circuitry (10) for performing phase measurements of the phase locked loop circuit and analog test circuitry (20) for testing at least one analog element of the phase locked loop circuit. Frequency measurement circuitry (30) is provided for performing frequency measurements of the phase locked loop circuit, as is circuitry (40) for performing calibration and jitter measurements. In this way cycle-to-cycle and phase jitter measurements may be made. A calibration mechanism is provided allowing a process evaluation to be made and which allows the jitter data to be provided in a few seconds. The fully digital design facilitates easy manufacture and ready retargeting of the module to diverse applications and processes.

      Abstract translation: 提供了用于测试锁相环电路的数字测试模块（5）。 模块（5）包括相位检测电路（10），用于执行锁相环电路和用于测试锁相环电路的至少一个模拟元件的模拟测试电路（20）的相位测量。 提供频率测量电路（30）用于执行锁相环电路的频率测量，电路（40）用于执行校准和抖动测量。 以这种方式，可以进行周期到周期和相位抖动测量。 提供了一种校准机制，允许进行过程评估，并且允许在几秒钟内提供抖动数据。 全数字化设计便于制造，并将模块准备好重新定位到各种应用和过程。

      Capacitive test point voltage and phasing detector
      86.
      发明授权
      Capacitive test point voltage and phasing detector 有权

      公开(公告)号：US06677741B2

      公开(公告)日：2004-01-13

      申请号：US10033118

      申请日：2001-10-26

      Applicant: Timothy R. Taylor

      Inventor： Timothy R. Taylor

      IPC: G01R3102

      CPC classification number: G01R25/00

      Abstract: Method and apparatus for accurately determining the presence of voltage at capacitive test points and for determining the phase angle relationship between two capacitive points. The detection of the presence of the voltage at the capacitive test points is independent of the voltage range in the systems, independent of the contamination or defects that may occur in the capacitive test point systems. The phase angle relationship is determined based on the actual phase angle difference between the voltage waveforms at the capacitive test points independent of the capacitive divider ratio difference and the capacitive test point voltage accuracy.

      Self-compensating phase detector
      87.
      发明授权
      Self-compensating phase detector 失效
      自补偿相位检测器

      公开(公告)号：US06518806B2

      公开(公告)日：2003-02-11

      申请号：US09782867

      申请日：2001-02-13

      Applicant: Luke A. Johnson

      Inventor： Luke A. Johnson

      IPC: H03L706

      CPC classification number: G01R25/00 ,  H03L7/081 ,  H03L7/087

      Abstract: A self compensating phase detector. Using two identical phase detectors introducing one of the phase detectors and a controlled variable phase shifter in a negative feedback loop shifts one clock signal enough such that the shifted signal compensates for existing static phase error. This self-compensation improves the accuracy of the phase difference measurement by significantly reducing the effect of static phase error. Moreover, this reduction remains true in spite of variations in process, temperature and voltage. Thus, inherent immunity of the invention to environmental conditions results in fewer failing parts during fabrication. Additionally, because the design is self-adjusting to environmental changes, design ease is significantly improved.

      Abstract translation: 自补偿相位检测器。 使用两个相同的相位检测器引入负反馈环路中的一个相位检测器和受控可变移相器，使一个时钟信号足够移动，使得移位的信号补偿现有的静态相位误差。 这种自我补偿通过显着降低静态相位误差的影响来提高相位差测量的精度。 此外，尽管工艺，温度和电压有变化，但这种降低仍然是正确的。 因此，本发明对环境条件的固有免疫力在制造过程中导致较少的故障部件。 另外，由于设计是对环境变化进行自我调整，因此设计容易度得到显着提高。

      Reflection coefficient phase detector
      88.
      发明申请
      Reflection coefficient phase detector 有权
      反射系数相位检测器

      公开(公告)号：US20020171411A1

      公开(公告)日：2002-11-21

      申请号：US09827719

      申请日：2001-04-06

      Inventor： Kevin P. Nasman

      IPC: G01R023/00

      CPC classification number: G01R25/00

      Abstract: A phase detector which determines the phase based upon the output signals from a power coupler. The power coupler outputs a first signal and a second signal. The first and second signals are input to a magnitude detector which determines the magnitude of the relative phase between the first and second signals. The first and second signals are also input to a sign discriminator which determines the sign of the phase between the first and second signals.

      Abstract translation: 相位检测器，其基于来自功率耦合器的输出信号确定相位。 功率耦合器输出第一信号和第二信号。 第一和第二信号被输入到幅度检测器，其确定第一和第二信号之间的相对相位的大小。 第一和第二信号也被输入到确定第一和第二信号之间的相位符号的符号鉴别器。

      Phase detector
      90.
      发明申请
      Phase detector 审中-公开
      相位检测器

      公开(公告)号：US20020057113A1

      公开(公告)日：2002-05-16

      申请号：US09928807

      申请日：2001-08-13

      Inventor： Ernst Mullner

      IPC: H03D013/00

      CPC classification number: H03K5/26 ,  G01R25/00 ,  H03D13/003

      Abstract: A phase detector wherein binary signals are supplied to inputs of an asymmetric circuit having two EXOR elements, the output voltage of the phase detector being proportional to the phase difference between the input signals by a subtraction of the output signals of two EXOR elements and subsequent low-pass filtering, and the subtraction is conducted in such a manner that there is no longer an error, due to the internal propagation delays of the EXOR elements, for determining the phase difference. In particular, the equal-phase condition between the input signals is determined accurately and by a simple voltage comparison with a threshold value selected by the expert, and the range of determination of greater phase differences between binary signals can be extended by the circuit proposed.

      Abstract translation: 相位检测器，其中二进制信号被提供给具有两个EXOR元件的非对称电路的输入，相位检测器的输出电压通过减去两个EXOR元件的输出信号和随后的低电平而与输入信号之间的相位差成比例 通过滤波，并且由于用于确定相位差的EXOR元件的内部传播延迟，不再有错误地进行减法。 特别地，准确地确定输入信号之间的等相状态，并且通过与由专家选择的阈值进行简单的电压比较来确定输入信号之间的等相条件，并且可以通过所提出的电路来扩展二进制信号之间较大相位差的确定范围。

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