公开(公告)号：US6011435A

公开(公告)日：2000-01-04

申请号：US778791

申请日：1997-01-06

申请人： Masato Takeyabu ,  Norio Murakami ,  Yasutaka Yamagata ,  Toshiyuki Sakai

发明人： Masato Takeyabu ,  Norio Murakami ,  Yasutaka Yamagata ,  Toshiyuki Sakai

IPC分类号： H04L25/02 ,  H03F3/45 ,  H03H11/04 ,  H03H11/12 ,  H04B3/14 ,  H04L25/03 ,  H04L25/52

CPC分类号： H03F3/45475 ,  H03F3/45766 ,  H03F2203/45291 ,  H03F2203/45528

摘要： A transmission-line loss equalizing circuit includes an equalizer, a gain control circuit for controlling the gain of the equalizer based upon the peak value of an equalized output, a slicer for slicing the equalized output and outputting a data pulse, a timing extraction pulse and an equalization control pulse, a DC feedback level detector for detecting a DC component of the equalized output and feeding the DC component back to the equalizer, and an attenuating circuit provided as an initial stage of the equalizer. A plurality of .sqroot.fAGC circuits constructing the equalizer are cascade-connected and constructed by a differential non-inverting amplifier.

摘要翻译： 传输线损耗均衡电路包括均衡器，用于基于均衡输出的峰值控制均衡器的增益的增益控制电路，用于对均衡输出进行分压并输出数据脉冲的限幅器，定时提取脉冲和 均衡控制脉冲，DC反馈电平检测器，用于检测均衡输出的DC分量并将DC分量馈送回均衡器;以及衰减电路，作为均衡器的初始级提供。 构成均衡器的多个2ROOT + E，rad f + EE AGC电路由差分同相放大器级联连接并构成。

公开(公告)号：USRE40168E1

公开(公告)日：2008-03-25

申请号：US10740901

申请日：2003-12-22

申请人： Hiromi Nanba ,  Tohru Mizutani ,  Makoto Ikeshita ,  Masato Takeyabu

发明人： Hiromi Nanba ,  Tohru Mizutani ,  Makoto Ikeshita ,  Masato Takeyabu

IPC分类号： H03K5/12

CPC分类号： G11C27/026 ,  H03F1/30 ,  H03F2200/453 ,  H03K5/2481 ,  H03K5/249 ,  H03K19/00384

摘要： An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD

摘要翻译： 评估电路16重复其输出VD被复位的处理，在电压Vi步进之后经过了各个时刻t 1和t 2之后，重复地获得复制电路11R的采样输出电压Vo之差 - 输入到复制电路11 R，并且将差值相继相加。 比较器电路20将差分累积电压VD与参考电压VS进行比较。 如果VD> VS，则偏置调整电路15在每给定时刻升压复制电路11R和调整电路11的偏置电流，并且如果VD

公开(公告)号：US06642871B2

公开(公告)日：2003-11-04

申请号：US10268157

申请日：2002-10-10

申请人： Masato Takeyabu ,  Yuji Kobayashi

发明人： Masato Takeyabu ,  Yuji Kobayashi

IPC分类号： H03M210

CPC分类号： H03M1/1061 ,  H03M1/442

摘要： The present invention relates to an analog/digital converter including an analog conversion unit including a plurality of stages having a pipelined configuration and a digital conversion unit. The digital conversion unit has digital-value storage registers, which are each provided for one of the stages. Each of the register is used for storing a digital value completing error correction for each segment, and adapted to output the digital value that corresponds to a segment number. The digital conversion unit also has an error-computation control unit, which controls the stages so that a specific one of the stages, inputs an error computation analog signal. The error-computation control unit then computes an error of the specific stage on the basis of digital-converted data computed from the digital values corresponding to segment numbers received from all the stages following the specific stage.

摘要翻译： 本发明涉及包括具有流水线配置的多个级的模拟转换单元和数字转换单元的模拟/数字转换器。 数字转换单元具有数字值存储寄存器，每个存储寄存器分别用于其中一个级。 每个寄存器用于存储每个段的数字值完成错误校正，并且适于输出对应于段号的数字值。 数字转换单元还具有误差计算控制单元，其控制级，使得特定的一级输入错误计算模拟信号。 然后，误差计算控制单元基于从与特定级之后的所有级接收到的段号对应的数字值计算出的数字转换数据，计算出特定级的误差。

公开(公告)号：US06535039B2

公开(公告)日：2003-03-18

申请号：US09921578

申请日：2001-08-06

申请人： Hiromi Nanba ,  Tohru Mizutani ,  Makoto Ikeshita ,  Masato Takeyabu

发明人： Hiromi Nanba ,  Tohru Mizutani ,  Makoto Ikeshita ,  Masato Takeyabu

IPC分类号： H03K512

CPC分类号： G11C27/026 ,  H03F1/30 ,  H03F2200/453 ,  H03K5/2481 ,  H03K5/249 ,  H03K19/00384

摘要： An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD

公开(公告)号：US06775524B2

公开(公告)日：2004-08-10

申请号：US10024610

申请日：2001-11-01

申请人： Masato Takeyabu ,  Yasuaki Takeuchi ,  Yuji Kobayashi ,  Seiji Miyoshi ,  Masahisa Yoshimi

发明人： Masato Takeyabu ,  Yasuaki Takeuchi ,  Yuji Kobayashi ,  Seiji Miyoshi ,  Masahisa Yoshimi

IPC分类号： H01Q1112

CPC分类号： H04L27/0002 ,  H04L27/2614 ,  H04L27/2626

摘要： When a transmission-line driver circuit that transmits a signal to a transmission line is supplied with a power-supply voltage from a power-supply circuit, the value of the power-supply voltage is controlled based upon the amplitude of a signal output from the transmission-line driver circuit. For example, the maximum value of a signal input to the transmission-line driver circuit in time units delimited at fixed time periods is detected, the target value of power-supply voltage supplied to the transmission-line driver circuit is decided based upon the maximum value, and the power-supply circuit is controlled in such a manner that the target value of power-supply voltage and actual value of power-supply voltage will agree.

摘要翻译： 当向传输线发送信号的传输线驱动电路被从电源电路提供电源电压时，电源电压的值根据从 传输线驱动电路。 例如，检测以固定时间段限定的时间单位输入到传输线驱动电路的信号的最大值，基于最大值决定提供给传输线驱动电路的电源电压的目标值 值，电源电路以电源电压的目标值和电源电压的实际值一致的方式进行控制。

公开(公告)号：US06392494B2

公开(公告)日：2002-05-21

申请号：US09115952

申请日：1998-07-15

申请人： Masato Takeyabu ,  Akira Kikuchi ,  Toshiyuki Sakai

发明人： Masato Takeyabu ,  Akira Kikuchi ,  Toshiyuki Sakai

IPC分类号： H03L7087

CPC分类号： H03L7/0805 ,  G01R25/00 ,  H03D13/001 ,  H03L7/07 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/0893 ,  H03L7/14 ,  H04L7/033

摘要： A frequency comparator includes a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively. The first and second detection signals are output for respective times based on a difference between the frequencies of the first and second clocks.

摘要翻译： 频率比较器包括电路，与第一和第二时钟之间的相位关系独立地比较第一和第二时钟的频率，并且当第一时钟分别具有高于和低于第二时钟的频率时，输出第一和第二检测信号 。 基于第一和第二时钟的频率之间的差，输出第一和第二检测信号各自的时间。